High-Density Flash Memory Device With Dual Metal Layer Routing
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Solution Overview
Problem
High-density NAND flash memory devices face challenges in reducing programming errors due to the 'tail-bit problem' caused by the need for multiple programming sessions, which can lead to dielectric breakdown and reliability issues due to low word line pitch.
Innovation Solution
The memory device structure reduces the number of string select lines in one memory block and employs two separate metal layers for routing lines to control units, ensuring satisfactory word line pitch and preventing dielectric breakdown, thereby improving reliability and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of string select lines is reduced in one memory block, then programming errors are reduced and the tail-bit problem is prevented, but the word line pitch becomes low which may cause dielectric breakdown
Solution Approach 1:
The patent introduces a second metal layer to route additional signal lines (string select lines, common source lines, dummy word lines, ground select lines, and inversion word lines) that are coupled to control units. This vertical dimensionality change allows more lines to be routed without increasing the planar word line pitch, thereby maintaining reliable programming operations while preventing dielectric breakdown.
2Quantity of substance
If multiple signal lines are routed in a single metal layer, then routing density is high, but the word line pitch becomes low causing dielectric breakdown in memory cells
Solution Approach 1:
The patent segments the routing of signal lines into two separate metal layers. The first metal layer routes a first group of lines, while the second metal layer routes a second group of lines. This segmentation distributes the routing density across multiple layers, maintaining adequate word line pitch and preventing dielectric breakdown while still achieving high overall routing capacity.
3Productivity
If the word line pitch is reduced to increase memory density, then more memory cells fit on chip, but dielectric breakdown occurs reducing device reliability
Solution Approach 1:
The patent utilizes a second metal layer to route additional signal lines, enabling high memory density through efficient space utilization in the vertical dimension. This allows the word line pitch to remain sufficiently large in the planar dimension to prevent dielectric breakdown, while still achieving high density through multi-layer routing architecture.
Data Source
AI summary
A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.