ESD Protection Circuit Area Reduction via Current Mirror Transistor Sizing
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the area occupied by ESD protection elements while maintaining effective electrostatic discharge resistance, particularly due to the need for high values of resistive and capacitive elements in RC time constant configurations.
Innovation Solution
A semiconductor device design incorporating a protection circuit with a first transistor, a resistive element, a second transistor forming a current mirror circuit, and a capacitive element, where the gate width of the second transistor is narrower than the first transistor, allowing for area reduction while maintaining ESD resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high values of resistive element R and capacitive element C are used in RC time constant configuration, then ESD protection performance is improved, but area occupied by the protection circuit increases
Solution Approach 1:
The patent changes the configuration parameters of the protection circuit by using a current mirror circuit with transistors having different gate widths (first transistor with gate width W1, second transistor with gate width W2 where W2 < W1). This allows the circuit to achieve effective ESD protection with smaller resistance and capacitance values, thereby reducing the occupied area while maintaining protection performance.
Solution Approach 2:
The protection circuit is segmented into functional modules: a first transistor coupled with a resistive element, a second transistor forming a current mirror, and a capacitive element. This segmentation allows each component to be optimized independently, with the current mirror circuit controlling current distribution to achieve effective ESD protection with reduced component values and smaller area.
2Area of moving object
If area of I/O block is reduced to decrease device size, then device integration density is improved, but ESD protection capability may be compromised
Solution Approach 1:
By changing the circuit topology to use a current mirror configuration with controlled gate widths, the patent achieves effective ESD protection with significantly reduced resistance and capacitance values. This allows the protection circuit to occupy less area within the I/O block, enabling higher integration density while maintaining ESD protection capability.
Solution Approach 2:
The patent merges the ESD protection function with the existing I/O block structure by integrating the protection circuit directly into the I/O cell. The current mirror circuit shares control nodes and power/ground connections with the I/O block, allowing ESD protection to be provided without adding significant area overhead to the I/O block.
Data Source
AI summary
Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.