Wafer Level Image Sensor Packaging with Opaque Encapsulation
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Solution Overview
Problem
Traditional image sensor packaging methods, such as COB and CSP, result in large, high-height structures with side light leakage issues, high costs, and complex manufacturing processes, making them unsuitable for compact, high-resolution applications.
Innovation Solution
A wafer level image sensor packaging structure using a TSV silicon wafer without metal wires or substrates, employing opaque encapsulation compounds around transparent lids to prevent side light leakage, simplifying the manufacturing process and reducing material usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional COB or CSP packaging methods are used, then the image sensor can be packaged, but the packaging structure becomes large in size and has significant height
Solution Approach 1:
The patent merges the substrate function and sensor chip mounting into a single integrated wafer structure. The TSV wafer serves as both the substrate and the sensor array carrier, eliminating the need for separate substrate and chip components. This integration directly reduces the overall packaging structure volume and complexity.
Solution Approach 2:
The patent transitions from traditional planar packaging to three-dimensional vertical integration using Through-Silicon Vias (TSV). Electrical connections are established through the wafer thickness rather than lateral wire bonds, enabling compact stacking and significantly reducing the horizontal footprint of the packaging structure.
2Object-affected harmful factors
If traditional CSP process is used, then packaging is achieved, but side light leakage occurs requiring additional shadow masks or shading material
Solution Approach 1:
The patent extracts and eliminates the shadow mask component entirely from the packaging structure. Instead of adding shading material to block side light, the design modifies the lens array configuration and packaging geometry to inherently prevent side light from reaching the photosensitive elements, thereby removing the harmful component rather than compensating for it.
Solution Approach 2:
The patent converts the potential harm of side light leakage into a beneficial compact packaging design. By using the TSV wafer structure and strategic placement of lenses and photosensitive elements, the packaging geometry itself creates natural light blocking, turning the packaging structure from a potential source of light leakage into an active element that prevents it.
3Loss of substance
If traditional COB packaging with metal wires and substrates is used, then electrical connections are established, but material usage increases and costs rise
Solution Approach 1:
The patent combines multiple functions into the TSV wafer structure: the wafer serves as substrate, conductor carrier, and mechanical support simultaneously. This eliminates the need for separate metal wire bonds and substrate materials, directly reducing material usage while maintaining electrical connectivity functions.
Solution Approach 2:
The patent changes the electrical connection method from lateral wire bonds to vertical through-wafer vias. This parameter change in connection geometry eliminates the need for extensive metal wiring and simplifies the manufacturing process by enabling direct bonding and automated assembly techniques.
4Productivity
If traditional packaging processes are used, then image sensors are packaged, but the manufacturing process is complex and production yield rate is reduced
Solution Approach 1:
The patent segments the manufacturing process into distinct modular stages: wafer preparation with TSV formation, lens array attachment, sensor chip mounting, and final packaging. This segmentation allows each module to be optimized independently and facilitates parallel processing, improving production yield while reducing overall process complexity.
Solution Approach 2:
The patent performs preliminary preparation of the TSV wafer structure, including via formation and conductor deposition, before final assembly. This preliminary action enables subsequent steps to be simpler and more reliable, reducing manufacturing complexity and improving yield by preventing defects early in the process.
Data Source
AI summary
The present invention discloses a wafer level image sensor packaging structure and a manufacturing method for the same. The manufacturing method includes the following steps: providing a silicon wafer with image sensor chips, providing a plurality of transparent lids, allotting one said transparent lid on top of the corresponding image sensor chip, and carrying out a packaging process. The manufacturing method of the invention has the advantage of having a simpler process, lower cost, and higher production yield rate. The encapsulation compound arranges on the first surface of the image sensor chip and covers the circumference of the transparent lid to avoid the side light leakage as traditional chip scale package (CSP). Thus, the sensing performance of the wafer level image sensor packaging structure can be enhanced.