Semiconductor Die Pad Layout for Straight Stacked Data Channels
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Solution Overview
Problem
Existing semiconductor die layouts face challenges in efficiently stacking multiple dies while maintaining independent communication channels and minimizing parasitic capacitance, complexity, and manufacturing costs.
Innovation Solution
The layout of data pads, dummy data pads, and common data pads on a die is optimized to allow for identical dies to be stacked with straight inter-layer connections, eliminating lateral-connection portions, which enables independent data channels and reduces complexity and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional die layouts are used for stacking, then manufacturing is simpler, but parasitic capacitance increases and independent communication channels are compromised
Solution Approach 1:
The patent segments the die layout into distinct regions with data pads positioned at opposite corners (e.g., top-left and bottom-right) and dummy data pads filling remaining corner positions. This segmentation allows straight vertical inter-layer connections to pass through dummy pads without lateral deviations, eliminating parasitic capacitance while maintaining independent communication channels for each die in the stack.
Solution Approach 2:
The patent uses dummy data pads as copies of real data pads in terms of physical structure and positioning, but these dummy pads are not electrically connected to any circuit. They serve as electrical through-holes that replicate the pad geometry needed for alignment, enabling straight vertical connections through stacked dies without introducing parasitic capacitance from lateral connection portions.
2Ease of manufacture
If lateral-connection portions are used in die stacking, then connectivity is achieved, but manufacturing complexity and costs increase
Solution Approach 1:
Instead of routing signals laterally across the die surface and then vertically through inter-layer connections, the patent inverts the approach by positioning data pads at corner locations that allow vertical connections to pass straight through dummy data pads. This eliminates the need for complex lateral-connection portions and reduces manufacturing complexity while achieving the same connectivity function.
3Reliability
If data pads are positioned for optimal circuit connection, then electrical performance is improved, but stacking alignment and independent channels are compromised
Solution Approach 1:
The patent employs asymmetric positioning of data pads at specific corner locations (e.g., top-left and bottom-right corners) rather than symmetric distribution. This asymmetric arrangement, combined with dummy data pads at remaining corners, creates a unique layout pattern that enables straight vertical inter-layer connections while maintaining optimal electrical connection to circuits, thereby simplifying stacking alignment without compromising electrical performance.
Data Source
AI summary
Layouts of data pads and dummy data pads are disclosed. A die may include a number of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge. The die may further include a first number of data pads variously electrically coupled to the number of circuits and arranged proximate to the first edge and a first number of dummy data pads, not electrically coupled to the number of circuits, alternatingly arranged with the first number of data pads, and proximate to the first edge. The die may further include a second number of data pads arranged proximate to the third edge and a second number of dummy data pads, alternatingly arranged with the second number of data pads, and proximate to the third edge. Associated devices, systems, and methods are also disclosed.