Vertical-Gate Transistor Layout for FinFET-Like Noise Control
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Solution Overview
Problem
The high manufacturing cost of finFETs due to increased processing steps limits the adoption of low-noise, high-control transistors in electronic devices like CMOS image sensors, necessitating a cost-effective alternative that maintains performance.
Innovation Solution
A vertical-gate transistor with a gate electrode structure comprising a horizontal portion and first and second vertical portions, which surrounds the channel region, reducing noise and increasing control without significantly increasing manufacturing costs, by using a trench isolation structure and additional masking and removal steps compared to planar MOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If finFET structure is used to reduce noise and increase control, then transistor performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from a planar gate structure to a vertical gate structure that extends in the depth dimension. The gate electrode structure includes a horizontal portion and vertical portions that surround the channel region, providing three-sided control compared to the top-only control in planar devices. This dimensional change achieves finFET-like performance without requiring the complex fin formation process.
Solution Approach 2:
The gate electrode structure is segmented into distinct portions: a horizontal portion at the top and vertical portions extending downward. These segments are formed through separate masking and etching steps, allowing independent optimization of each portion's geometry and material composition while achieving the surrounding control effect.
2Object-affected harmful factors
If finFET manufacturing process is used to achieve low noise, then device performance is improved, but processing steps increase
Solution Approach 1:
The gate electrode structure is formed preliminarily before source/drain region creation. The horizontal and vertical gate portions are established first, defining the channel region geometry, and then source/drain regions are formed in the exposed semiconductor substrate areas. This preliminary gate formation simplifies subsequent processing compared to finFET methods.
3Reliability
If vertical gate structure surrounding channel region is implemented, then control and noise reduction are improved, but device complexity increases
Solution Approach 1:
The gate electrode structure serves multiple functions simultaneously: the horizontal portion provides top gate control while the vertical portions provide sidewall control, creating a multi-functional control system. This universal structure can be adapted to different channel widths and lengths without fundamental design changes, achieving versatility in control mechanisms.
Data Source
AI summary
In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.