3D Channel Semiconductor Layout With Bottom Isolation Contacts
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates improved electrical characteristics and reliability, particularly in semiconductor devices with Backside Power Delivery Network (BSPDN) structures and three-dimensional channel structures to overcome size reduction limitations.
Innovation Solution
A semiconductor device design featuring an insulating base layer with fin-type patterns, channel structures, gate structures, source/drain patterns, internal spacers, and bottom isolation patterns, along with lower contact structures that penetrate the base layer to enhance electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to increase integration density, then productivity and integration degree improve, but electrical characteristics and reliability deteriorate
Solution Approach 1:
The patent transitions from planar channel structures to three-dimensional channel structures, utilizing vertical stacking of channel layers to increase integration density while maintaining effective channel length and electrical characteristics. This dimensional change allows higher transistor density without proportionally reducing device performance.
Solution Approach 2:
The patent implements nested structures where gate structures surround channel structures in a wrap-around configuration, and multiple channel layers are stacked vertically within a compact footprint. This nesting approach maximizes the use of available space while maintaining proper electrical isolation and control.
2Reliability
If complex three-dimensional channel structures are implemented to overcome size limitations, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
The patent divides the channel structure into multiple discrete channel layers stacked vertically, with gate structures controlling each layer. This segmentation allows independent optimization of each channel layer and simplifies the manufacturing process by enabling modular fabrication approaches.
Solution Approach 2:
The gate structures serve multiple functions: they control the electrical characteristics of channel structures, provide mechanical support for the stacked configuration, and enable scaling to different device densities. This multi-functionality reduces the need for additional specialized components.
3Reliability
If lower contact structures penetrate through isolation patterns to connect source/drain patterns, then electrical connectivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms lower contact structures that penetrate through bottom isolation patterns to connect source/drain patterns before subsequent processing steps. This preliminary connection establishment ensures proper electrical connectivity is achieved early in the fabrication sequence, guiding subsequent alignment and patterning operations.
Solution Approach 2:
The bottom isolation patterns serve as intermediary structures that are selectively removed to create pathways for lower contact structures. These intermediary elements facilitate the formation of electrical connections while maintaining isolation in other regions, acting as temporary guides during the manufacturing process.
Data Source
AI summary
A semiconductor device includes an insulating base layer, a fin-type pattern on the insulating base layer and extending in a first direction, a plurality of channel structures on the fin-type pattern and spaced apart from each other in the first direction, each of the plurality of channel structures including a plurality of channel layers spaced apart from each other in a second direction that is perpendicular to the first direction, a plurality of gate structures respectively on the plurality of channel structures and extending in a third direction intersecting the first direction, source/drain patterns including a first source/drain pattern that is connected to side surfaces of some of the plurality of channel structures, internal spacers between the plurality of gate structures and the source/drain patterns, and a plurality of bottom isolation patterns respectively below the plurality of gate structures and between the insulating base layer and the fin-type pattern.