Nanoinformatics TRIZ Cases

Photolithography forms wafer-scale nano-gap electrode arrays that suspend 2D materials, reducing substrate scattering and improving mobility.

Necked nanowires in gate-all-around transistors improve short-channel control and threshold tuning without adding complex fabrication steps.

Bridge portions connect adjacent gate lines to resist collapse during fabrication, preserving structural integrity in dense multi-gate transistors.

An atomic-layer junction barrier film around nanowire source/drain regions lowers Schottky resistance without silicon-consuming silicide formation.

A head-and-body separation pattern adds insulating interfaces between channel patterns to suppress short-channel leakage and protect MOSFET reliability.

Horizontal offset between upper and lower channel structures opens contact space, cuts pitch, and supports higher transistor density.

Extension and protruding gate portions connect from the backside to cut contact aspect ratio, improving reliability and easing dense layout.

A vertically stacked MOSFET uses wraparound gates and a penetrating upper source/drain contact to raise density without degrading operation.

Etch-selective dummy patterns enable self-aligned vertical vias in stacked semiconductor channels, easing fabrication while improving density and electrical performance.

A dopant-graded source/drain and backside silicide lower Schottky barrier height and contact resistance in downscaled FETs.

Vertical nanosheet channel stacks with gate isolation and insulating layers help scaled ICs maintain accuracy while preventing short-circuits.

Self-aligned dielectric anchor voids ease nanowire gate plug etching, improve work function metal fill, and support gate isolation.

Jog structures over dummy gate stacks correct overlay shifts, reducing mushroom defects and electrical shorting in multi-gate nanosheet FETs.

Different nanowire stack counts in memory and logic regions improve SRAM Vmin while reducing metal-fill voids and protecting the gate interface.

A zigzag channel structure increases semiconductor integration while allowing channel width adjustment without increasing vertical height.

Rare-earth dielectric isolation between semiconductor structures reduces capacitance impact and current leakage in miniaturized IC layouts.

Separate n- and p-type silicide stacks with silicidation stop layers lower Schottky barriers and source/drain contact resistance in scaled FinFETs.

Different work function stacks across SRAM subarrays tune threshold voltage to balance fast access with low leakage power.

Controlled impurity region widths and sacrificial spacers improve ion implantation alignment to curb punch-through and transistor leakage.

Backside self-aligned penetrating contacts bypass lithography spacing limits in nanowire transistors, improving alignment and lowering defects.

A Si or SiGe barrier layer between recessed source/drain regions and epitaxial layers suppresses phosphorous diffusion in SiGe FinFETs.

A graded dummy region between cell areas smooths pattern density changes during CMP, reducing dishing, erosion, and line resistance.

A dielectric wall adds width-direction stress to forksheet channels, boosting carrier mobility alongside source/drain lengthwise stress.

An insulating sidewall layer isolates backside source/drain contacts from semiconductor material to cut leakage current and improve IC reliability.

Bottom isolation patterns and penetrating lower contacts improve BSPDN semiconductor connectivity, electrical characteristics, and reliability.

A dual-material spacer buffers crystal orientation mismatch in GAA nanosheet transistors, reducing source/drain dislocation and contact resistance.

Varying channel counts across stacked transistors improves density without uniformly sacrificing switching speed or stack-level performance.

Varying inner insulating widths around channel and gate regions suppresses parasitic capacitance and fixed charge effects in scaled MOSFETs.

A coplanar contact layout and single insulating layer prevent gate-contact shorts while lowering interfacial resistance in scaled semiconductor structures.

A dual-dielectric spacer in a stacked-channel GAA transistor boosts gate coupling while cutting gate-source/drain parasitic capacitance.

Backside wordlines linked by through vias improve SRAM signal routing speed while easing front-side wiring complexity and integration.

Void isolation patterns and double-sided interconnects cut parasitic capacitance and RC delay in dense 3D semiconductor layouts.

A sacrificial trench layer blocks gate wraparound on subfins, then backside dielectric replacement lowers parasitic capacitance and boosts switching speed.

A dielectric wall adds tensile or compressive stress in both channel directions to boost carrier mobility in forksheet nanosheet transistors.

Varying semiconductor pattern widths and isolation layers help scaled MOSFETs maintain operation characteristics with better layout freedom.

Controlled oxidation and annealing form semiconductor quantum dots inside an insulating layer, enabling precise placement and Si-compatible integration.

Different contact-isolation sidewall slopes improve source/drain contact formation in nanosheet transistors while preserving manufacturability.

Double pocket sidewall barriers and cell isolation layers create storage openings for denser 3D memory cells with lower parasitic capacitance.

Recessed source/drain openings and undoped-to-doped layers suppress mesa leakage in multi-gate transistors without sacrificing gate control.

A backside gate contact and top dielectric nanosheet cut gate-to-SAC parasitic capacitance and avoid contact-cap corner erosion.

Segmented fin spacers with etch stop patterns preserve etch margin and source/drain shape as semiconductor integration increases.

A segmented gate and substrate-linked channel suppress floating body effects in fin SOI transistors while preserving current and low leakage.

Combining NSFETs in NMOS regions with FinFETs in PMOS regions shrinks SRAM cells while reducing leakage, latch-up, and voltage mismatch.

A two-level gate isolation trench lowers gate-to-gate parasitic capacitance while preserving the gate fill window and yield.

An air gap above the source/drain contact cuts parasitic capacitance while preserving reliable contact formation in scaled semiconductor devices.

Concave mesa sidewalls in a GAA fin raise the leakage path resistance, cutting substrate leakage while preserving gate control and strength.

A segmented nanosheet MBCFET uses region-tuned source/drain doping and surround gates to curb leakage while preserving scaling and current control.

A gate pattern bridge stabilizes adjacent nanosheet gate electrodes at their boundary, improving alignment consistency and manufacturing yield.

Asymmetric source/drain shaping and lateral epitaxial growth improve contact fill, cut residue, and reduce capacitance overlap.

Thicker work function regions near protrusions raise parasitic threshold voltage and cut leakage in stacked gate-all-around transistors.