SRAM Subarray Work Function Tuning for Speed-Leakage Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM memory devices struggle to balance speed and power consumption due to all transistors having similar structure and work function layer arrangements, making it difficult to achieve optimal performance.
Innovation Solution
Implementing an SRAM array with at least two subarrays of transistors having similar dimensions but different work function stacks to meet design needs in terms of speed and low leakage, utilizing modularized work function arrangements for FinFETs and MBC transistors with varying threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all transistors have similar structure and work function layer arrangement, then manufacturing is simplified, but it becomes difficult to balance speed and power consumption
Solution Approach 1:
The patent applies local quality by implementing different work function layer arrangements in different regions of the SRAM array. Specifically, first subarrays have transistors with a first work function layer arrangement optimized for speed, while second subarrays have transistors with a second work function layer arrangement optimized for low leakage. This allows each region to have tailored properties for its intended function while maintaining overall manufacturing simplicity through modular design.
2Productivity
If transistors are scaled down to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the SRAM array into multiple subarrays with different work function layer arrangements. This modular approach allows the complex requirement of having different transistor characteristics to be broken down into manageable, repeatable units. Each subarray type can be manufactured using standardized processes, reducing overall processing complexity while achieving high functional density through compact integration of multiple subarray types.
3Adaptability or versatility
If transistors with different threshold voltages are implemented, then speed and power consumption can be optimized, but transistor structure complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the work function layer parameters (material composition, thickness, stacking sequence) to achieve different threshold voltages. Instead of creating fundamentally different transistor structures, the invention varies specific parameters of the work function layers - such as using different metal combinations (e.g., TiN, TaN, WN) or adjusting layer thicknesses - to tune threshold voltages while maintaining the same basic FinFET structure across all transistors.
Data Source
AI summary
Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.