Dual Silicide Contact Stack With Stop Layers for FinFET S/D Resistance
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Solution Overview
Problem
The scaling down of semiconductor devices increases complexity in manufacturing processes, particularly in forming contact structures with silicide layers that affect the Schottky barrier heights, leading to higher contact resistances between source/drain regions and contact structures in n-type and p-type FETs.
Innovation Solution
The formation of n-type and p-type silicide layers with work function values closer to the conduction and valence band energies of the respective S/D regions, respectively, is achieved by using nWFM and pWFM silicide layers, and the use of silicidation stop layers to prevent unwanted reactions, thereby reducing SBHs and contact resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional silicide layers are used in scaled-down semiconductor devices, then manufacturing processes become more complex, but contact resistances between source/drain regions and contact structures increase
Solution Approach 1:
The patent applies local quality by using different work function metal silicide layers (nWFM and pWFM) for n-type and p-type FETs respectively. The nWFM silicide layer has work function optimized for n-type S/D regions while pWFM silicide layer has work function optimized for p-type S/D regions, achieving locally optimized electrical properties for each device type rather than using a uniform silicide layer across all devices
Solution Approach 2:
The patent changes the work function parameter of the silicide layers by selecting different metal materials with appropriate work functions. The nWFM layer has work function closer to the conduction band energy of n-type S/D regions, while the pWFM layer has work function closer to the valence band energy of p-type S/D regions, thereby optimizing the Schottky barrier height and reducing contact resistance
2Reliability
If silicide layers are formed to reduce contact resistance, then Schottky barrier heights must be optimized, but this increases the complexity of forming different silicide layers for n-type and p-type FETs
Solution Approach 1:
The patent segments the silicide layer formation process into two distinct stages: first forming the nWFM silicide layer for n-type FETs, then forming the pWFM silicide layer for p-type FETs. This segmentation allows each silicide layer to be independently optimized for its respective device type while maintaining a systematic manufacturing approach
Solution Approach 2:
The patent uses an intermediary approach by introducing work function metal layers as intermediate structures between the S/D regions and the contact structures. These WFM layers serve as mediators that facilitate optimized electrical contact by matching the work function to the band structure of the underlying S/D regions, thereby reducing the Schottky barrier height
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistances and improves the performance of n-type and p-type FETs by aligning silicide layers with the band energies of the S/D regions, enhancing the electrical connectivity and reducing manufacturing complexity.
Implementation Method 1
The formation of n-type and p-type silicide layers with work function values closer to the conduction and valence band energies of the respective S/D regions, respectively, is achieved by using nWFM and pWFM silicide layers
Implementation Method 2
the use of silicidation stop layers to prevent unwanted reactions, thereby reducing SBHs and contact resistances
Data Source
AI summary
A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second oxidation stop layers on the n- and p-type S/D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers into first and second semiconductor oxide layers, respectively, forming a first silicide-germanide layer on the p-type S/D region, and forming a second silicide-germanide layer on the first silicide-germanide layer and on the n-type S/D region.