Dielectric Wall Stress Layout for Forksheet Nanosheet Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices, particularly forksheet transistors, face limitations in applying channel stress effectively in both the channel-width and channel-length directions, which affects carrier mobility and device performance.
Innovation Solution
The introduction of a dielectric wall that applies compressive or tensile stress to the channel structure based on the polarity type and surface orientation of nanosheet transistors, allowing stress application in both the channel-width and channel-length directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric wall is introduced to apply channel stress in both channel-width and channel-length directions, then carrier mobility and device performance are enhanced, but device structure and manufacturing process become more complex
Solution Approach 1:
A dielectric wall is introduced as an intermediary structure between the two nanosheet transistors in the forksheet configuration. This dielectric wall serves as a mediator to apply channel stress to the channel structures in both the channel-width and channel-length directions, thereby enhancing carrier mobility and device performance without requiring direct modification of the transistor cores
Solution Approach 2:
The dielectric wall is strategically positioned to apply stress locally to specific regions of the channel structure. By configuring the dielectric wall between the two nanosheet transistors, stress is applied precisely where needed - to the channel surfaces in both width and length directions - rather than uniformly across the entire device, optimizing the stress application efficiency
2Reliability
If channel stress is applied to increase carrier mobility, then device performance improves, but the ability to apply stress effectively in both channel-width and channel-length directions is limited in existing structures
Solution Approach 1:
The invention transitions from applying stress in a single direction to applying stress in multiple dimensions. The dielectric wall configuration enables stress application in both the channel-width direction (lateral stress) and the channel-length direction (longitudinal stress), creating a three-dimensional stress state that enhances carrier mobility more effectively than conventional single-direction stress application
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and improves device performance by optimizing stress application in forksheet transistors, leading to increased mobility of electrons or holes depending on the transistor's polarity and surface orientation.
Implementation Method 1
a dielectric wall applied a tensile stress to channel structures of the first and second nanosheet transistors in a 2nd direction parallel to a substrate surface along which carriers moved in the channel
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
Provided is a semiconductor device which includes: a 1st channel structure extended in a 1st direction; a 1st source/drain pattern on the 1st channel structure; a 2nd channel structure extended in the 1st direction wherein the 2nd channel structure is disposed at a side of the 1st channel structure in a 2nd direction intersecting the 1st direction; a 2nd source/drain pattern on the 2nd channel structure; and a 1st dielectric wall between the 1st channel structure and the 2nd channel structure. In a first alternative, the 1st source/drain pattern and the 2nd source/drain pattern are each of n-type, and a top surface of each of the 1st channel structure and the 2nd channel structure is in a (110) orientation and a side surface of each of the 1st channel structure and the 2nd channel structure is in a (100) orientation, respectively. In a second alternative, the 1st source/drain pattern and the 2nd source/drain pattern are each of p-type, wherein a top surface of each of the 1st channel structure and the 2nd channel structure is in a (100) orientation, and wherein a side surface of each of the 1st channel structure and the 2nd channel structure is in a (110) orientation.