Multi-Stack Transistor Channel Layout for Density and Speed Balance
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Solution Overview
Problem
The challenge is to enhance the performance and speed of semiconductor devices with multi-stack transistor structures while optimizing the density of transistors in a limited space on a substrate.
Innovation Solution
A semiconductor device with varying numbers of channel layers in each transistor stack is designed, where the number of lower and upper channel layers in each stack is differently configured to suit the characteristics of individual transistors, and slits are used to remove portions of gate structures, filled with insulating material, to optimize performance and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of channel layers is increased in multi-stack transistor structures, then the density of transistors in limited space is improved, but the performance and speed of individual transistors may deteriorate due to increased complexity and interference between stacks
Solution Approach 1:
The patent applies local quality by configuring different numbers of channel layers in different transistor stacks based on their specific functional requirements. Some stacks have more channel layers to increase density for certain circuit functions, while other stacks have fewer channel layers to maintain better performance and speed characteristics, thereby optimizing both density and performance locally across the semiconductor device.
Solution Approach 2:
The patent utilizes parameter changes by varying the number of channel layers as a key parameter across different transistor stacks. This allows the device to optimize the balance between transistor density and performance/speed by adjusting this critical structural parameter according to the specific needs of different circuit regions, rather than using a uniform configuration throughout.
2Reliability
If the number of channel layers is varied across different transistor stacks, then the performance and speed of individual transistors is improved, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into multiple transistor stacks with different channel layer configurations. Each stack can be independently designed and optimized for specific performance requirements, allowing the manufacturing process to handle varied configurations through systematic segmentation rather than attempting to manufacture all stacks with identical uniform structures.
Solution Approach 2:
The patent utilizes dynamics by implementing flexible configurations where the number of channel layers can be dynamically adjusted in different stacks based on performance requirements. This dynamic approach allows the device to adapt to different circuit design needs while managing manufacturing complexity through planned variability rather than rigid uniformity.
3Reliability
If slits are formed to remove portions of gate structures, then the performance and speed of transistors is optimized, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies the taking out principle by forming slits to remove specific portions of gate structures in selected transistor stacks. This extraction of unnecessary gate structure material allows for optimized transistor performance and speed by reducing interference between adjacent stacks, while the precision requirements are managed by targeting specific removal zones rather than requiring perfect precision across the entire gate structure.
Solution Approach 2:
The patent utilizes local quality by applying slit formation selectively to specific regions of the gate structures where it is most beneficial for performance optimization. Rather than uniformly modifying all gate structures, the slits are localized to specific stacks or regions, allowing precision to be concentrated where most needed while reducing overall manufacturing complexity.
Data Source
AI summary
A semiconductor device according to various embodiments includes a substrate and a plurality of transistor stacks formed on the substrate. Each of the transistor stacks includes a lower transistor including at least one lower channel layer and a lower gate structure enclosing the at least one lower channel layer and formed on the substrate, and an upper transistor including at least one upper channel layer and an upper gate structure enclosing the at least one upper channel layer and formed on the lower transistor. A sum of a number of first lower channel layers and a number of first upper channel layers of a first transistor stack is different from a sum of a number of second lower channel layers and a number of second upper channel layers of a second transistor stack.