Multi-Layer Channel Line Isolation for Scaled IC Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit devices face challenges in maintaining operation speed and accuracy as they are scaled down, requiring stable conductive line configurations and insulating structures to prevent short-circuits in a limited area.
Innovation Solution
A method of manufacturing an integrated circuit device involving the formation of multi-layer channel lines through alternating deposition of nanosheets and sacrificial layers, followed by etching and spacer formation, to create a reliable and efficient structure with insulating layers and gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuit devices are scaled down to increase efficiency, then productivity and operation speed are improved, but manufacturing precision and reliability deteriorate due to difficulty in securing stable operation accuracy
Solution Approach 1:
The channel line is divided into multiple nanosheets arranged in a multi-layer structure (e.g., three layers: lower, intermediate, and upper channel lines). Each nanosheet is formed by alternating deposition of semiconductor layers and sacrificial layers, followed by selective removal. This segmentation allows the channel to maintain sufficient width and control characteristics even when the overall device size is reduced, thereby preserving operation accuracy while enabling device scaling for improved productivity.
2Productivity
If the wiring structure is made more compact to fit in a smaller area, then productivity increases, but reliability worsens due to increased risk of short-circuit effects between conductive regions
Solution Approach 1:
The patent transitions from a planar wiring structure to a three-dimensional multi-layer channel line structure. Multiple channel lines are stacked vertically with insulating structures between layers, allowing conductive paths to be arranged in different spatial dimensions. This vertical stacking enables compact area utilization while maintaining adequate spacing between conductive regions through the insulating layers, thus preventing short-circuits while improving area efficiency.
Solution Approach 2:
Insulating structures are introduced as intermediary layers between adjacent and stacked channel lines. These insulating structures fill the spaces between nanosheets and around the channel formation regions, providing electrical isolation between conductive regions. This intermediary insulation prevents short-circuit effects while allowing the wiring structure to be compactly arranged for improved productivity.
3Manufacturing precision
If multi-layer channel lines are formed by alternating deposition of nanosheets and sacrificial layers, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Sacrificial layers are deposited alternately with semiconductor layers in a preliminary sequence before the final channel structure is formed. These sacrificial layers serve as placeholders that define the precise positions and thicknesses of the future channel regions. After the multi-layer structure is completely formed, the sacrificial layers are selectively removed to create the desired channel configuration. This preliminary action enables precise control of channel line dimensions and arrangements while managing the complexity of the deposition process.
Solution Approach 2:
The sacrificial layers are temporarily introduced during the deposition process to enable precise formation of the multi-layer channel structure, then selectively removed in a subsequent step. This temporary material serves its purpose during fabrication and is then discarded to reveal the final channel configuration. This approach allows complex multi-layer structures to be formed with high precision without permanently increasing the device complexity, as the sacrificial materials are eliminated after serving their formation function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the operating characteristics and structural stability of integrated circuit devices, improving reliability and efficiency.
Implementation Method 1
forming a lower channel stack extending in a first horizontal direction, by alternately vapor-depositing a plurality of lower nanosheets and a plurality of lower sacrificial layers on the substrate
Data Source
AI summary
A method of manufacturing an integrated circuit device includes sequentially forming a lower channel stack, an intermediate layer, and an upper channel stack on a substrate, forming a recess space by removing portions of the lower and upper channel stacks, and the intermediate layer, forming, sequentially, an insulating layer, a lower source/drain region and an upper source/drain region in the recess space, removing a sacrificial layer included in the lower and upper channel stacks and the intermediate layer, and forming a lower gate insulating layer on the lower channel stack and an upper gate insulating layer on the upper channel stack, forming a lower gate line on the lower gate insulating layer and an upper gate line on the upper gate insulating layer, and forming a gate isolation structure after the forming of the lower gate line and before the forming of the upper gate line.