Semiconductor Contact Layout for Low-Resistance Gate Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges with shorts between source/drain contacts and gate electrodes, as well as high interfacial resistance between these components and wiring patterns, which hinder efficient operation and scaling.
Innovation Solution
The semiconductor device design includes a unique structure where source/drain contacts and gate electrodes are formed at varying heights, with a single interlayer insulating layer covering both, eliminating separate vias and reducing interfacial resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate vias are formed between source/drain contacts and wiring patterns, then connection reliability is improved, but interfacial resistance increases and device complexity increases
Solution Approach 1:
The patent merges the source/drain contact and gate electrode into a coplanar structure where both are formed at the same height level on the semiconductor substrate. This eliminates the need for separate via connections between different height levels, reducing interfacial resistance and device complexity while maintaining connection reliability through direct planar contact with wiring patterns
2Device complexity
If source/drain contact and gate electrode are at the same height, then interfacial resistance is reduced, but shorts may occur between them
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the source/drain contact and gate electrode regions. This insulating layer is positioned to electrically isolate the two conductive elements that are at the same height level, preventing shorts while allowing both to maintain low interfacial resistance with the wiring patterns through direct planar contact
3Reliability
If multiple interlayer insulating layers are used to cover source/drain regions, then isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a single interlayer insulating layer that performs multiple functions simultaneously: it isolates the source/drain regions, supports the coplanar gate electrode structure, and provides a uniform surface for wiring pattern formation. This multi-functional approach achieves adequate isolation while significantly reducing manufacturing complexity compared to multiple separate insulating layers
Data Source
AI summary
A semiconductor device may include an active pattern on a substrate, first to third gate electrodes on the active pattern, a first source/drain region and a first source/drain contact between the first and second gate electrodes, a second source/drain region and a second source/drain contact between the second and third gate electrodes, a gate spacer on both sidewalls of the second gate electrode, a first interlayer insulating layer covering the first and second source/drain regions, and a second interlayer insulating layer in contact with at least a portion of sidewalls of the first source/drain contact. A lower surface of the second interlayer insulating layer may contact upper surfaces of the second gate electrode, the second source/drain contact, and the gate spacer between the second gate electrode and the second source/drain contact.