Nanosheet MBCFET Source/Drain Structure for Leakage Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling density and improving current control capabilities while effectively suppressing short channel effects, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a multi-bridge channel field effect transistor (MBCFET) design featuring a first active pattern with a first lower pattern and sheet patterns, source/drain patterns, and gate structures, including specific regions and recesses to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-gate transistor with three-dimensional channel is used to increase device density, then scaling capability is improved, but leakage current increases and reliability deteriorates
Solution Approach 1:
The channel is segmented into multiple discrete nanosheets arranged in series, with each nanosheet forming part of the conduction path. This segmentation allows independent control of each nanosheet region and enables better suppression of leakage current while maintaining the three-dimensional structure for high density.
Solution Approach 2:
Different regions of the source/drain pattern are given different impurity concentrations and types. The first region has a first impurity concentration while the second region has a second impurity concentration different from the first, allowing localized optimization of electrical properties to reduce leakage current in specific areas.
2Reliability
If gate length is increased to improve current control capability, then current control is improved, but device scaling is restricted
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional configuration where gate electrodes surround the nanosheet channel from multiple sides. This dimensional change provides enhanced current control capability through better electrostatic control without increasing the gate length, thus maintaining scalability.
3Reliability
If short channel effects are suppressed by increasing gate length, then short channel effect suppression is improved, but device density decreases
Solution Approach 1:
By forming gate electrodes that surround the nanosheet channel in three dimensions rather than using a planar gate, the patent achieves enhanced short channel effect suppression through improved electrostatic control. This allows maintaining short gate lengths while still effectively suppressing SCE, thereby preserving high device density.
Data Source
AI summary
A semiconductor device is provided. A semiconductor device comprising a first active pattern including a first lower pattern and a plurality of first sheet patterns spaced apart from the first lower pattern in a first direction and having a first source/drain recess formed therein, a first source/drain pattern filling the first source/drain recess and in contact with the first sheet patterns on the first lower pattern, and first gate structures disposed on both sides of the first source/drain pattern in a second direction different from the first direction and each including first gate electrodes each surrounding the plurality of first sheet patterns, wherein the first source/drain pattern includes a first region on the first lower pattern, second regions including impurities of a conductivity type different from that of the first region and in contact with the first region and side surfaces of the first sheet patterns, and a third region between the second regions, and a thickness of the first region in the first direction is greater than a thickness of the second region.