Gate-All-Around Transistor Layout With Variable Work Function Thickness

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Solution Overview

Problem

Existing semiconductor devices with gate-all-around transistors suffer from high leakage current due to insufficient gate control over protrusions, which is exacerbated by the difficulty in controlling ion diffusion during doping processes.

Innovation Solution

The semiconductor structure incorporates work function layers surrounding channel layers with a specific material choice (P-type for NMOS, N-type for PMOS) and varying thicknesses, along with sacrificial layers of different thicknesses to form through grooves, enhancing threshold voltage and reducing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate-all-around transistors are used to increase component density and integration, then transistor control over channel is improved, but leakage current increases due to insufficient gate control over protrusions

Engineering Contradiction:
Improvetransistor control capabilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by introducing work function layers with different thicknesses at different locations. Specifically, the work function layer has a first thickness at regions adjacent to protrusions and a second thickness at other regions, where the first thickness is greater than the second thickness. This local variation in work function layer thickness creates different threshold voltages for parasitic devices at different locations, thereby reducing leakage current from protrusions while maintaining device performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of work function layer thickness to control threshold voltage. By making the work function layer thicker at regions adjacent to protrusions, the threshold voltage of parasitic devices at those regions is increased, making them less likely to turn on and reducing leakage current. This parameter change is implemented through varying the thickness of the work function layer across different regions of the semiconductor device.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If work function layers with varying thicknesses are introduced to reduce leakage current, then threshold voltage control is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidwork function layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the work function layer into different thickness regions. The work function layer is designed with a first thickness at regions adjacent to protrusions and a second thickness at other regions. This segmentation allows different parts of the device to have different threshold voltage characteristics, enabling reduced leakage current from protrusions while maintaining overall device functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces variation in the vertical dimension (thickness) of the work function layer to achieve different threshold voltages. Instead of using a uniform thickness, the work function layer thickness is varied in the vertical dimension across different horizontal regions, allowing for differential control of parasitic device threshold voltages without adding lateral structural complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250374662A1Semiconductor structure and fabrication method thereof
Publication Date: 2025.12.04 SEMICON MFG INT (SHANGHAI) CORP
  • US20250374662A1 patent drawing
  • US20250374662A1 patent drawing
  • US20250374662A1 patent drawing

AI summary

A semiconductor structure includes: a substrate; and gate-all-around transistors on the substrate. Each gate-all-around transistor includes: a discrete protrusion on the substrate; a channel structure layer spaced apart from and suspended on the protrusion, including channel layers longitudinally stacked at intervals along a direction perpendicular to a surface of the substrate, a distance between the protrusion and a channel layer adjacent to the protrusion being larger than a distance between adjacent channel layers along the direction perpendicular to the surface of the substrate; a gate structure crossing the channel structure layer and surrounding each channel layer in the channel structure layer; a gate dielectric layer between the gate structure and the channel layers, and between the gate structure and the protrusion; and source-drain doped regions on the protrusion at two sides of the gate structure and in contact with ends of each channel layer along an extension direction.