GAA Transistor Spacer Layout for Lower Gate-Drain Capacitance
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Solution Overview
Problem
The parasitic capacitance between the gate and source/drain in nano gate-all-around field effect transistors (GAA-FETs) leads to reduced operation speed, which is a challenge in miniaturized integrated circuits.
Innovation Solution
A semiconductor device design featuring a channel layer stacking portion surrounded by a gate-all-around structure, isolated by a spacer structure comprising a first spacer with a high dielectric constant and a second spacer with a low dielectric constant, reducing parasitic capacitance and enhancing electric field coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a gate-all-around structure is used to improve gate control, then driving current per unit projection area increases, but parasitic capacitance between gate and source/drain increases
Solution Approach 1:
The spacer structure is divided into two segments: a first spacer made of high dielectric constant material and a second spacer made of low dielectric constant material. This segmentation allows the first spacer to provide strong electric field coupling for high driving current, while the second spacer provides electrical isolation to reduce parasitic capacitance between the gate and source/drain regions.
Solution Approach 2:
Different regions of the spacer structure are assigned different dielectric properties. The first spacer region (adjacent to the channel) uses high dielectric constant material to enhance gate control and driving current, while the second spacer region (adjacent to source/drain) uses low dielectric constant material to minimize parasitic capacitance. This local differentiation resolves the contradiction between needing strong coupling and low parasitic capacitance.
2Productivity
If feature size is decreased to achieve miniaturization, then integration density increases, but parasitic capacitance effects become more significant
Solution Approach 1:
The spacer structure uses a composite of two different dielectric materials with contrasting properties. The high dielectric constant material (e.g., HfO2, TiO2) provides strong electric field coupling in the critical region near the channel, while the low dielectric constant material (e.g., SiO2, air gap) provides electrical isolation in the region near the source/drain. This composite approach enables continued miniaturization while controlling parasitic capacitance effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves operation speed and driving performance by minimizing parasitic capacitance while maintaining effective electric field coupling, thus enhancing the performance of the semiconductor device.
Implementation Method 1
a dielectric constant of a material of the first spacer is greater than a dielectric constant of a material of the second spacer
Implementation Method 2
the parasitic capacitance between the gate and the source/drain is large, which will significantly reduce the operation speed of the circuit
Data Source
AI summary
The present disclosure provides a semiconductor device, a method, and an electronic apparatus. The device includes: a substrate; a channel layer stacking portion including multiple channel layers along a thickness direction of the substrate, a length direction of the channel layer is perpendicular to the thickness direction of the substrate, and the channel layer includes a first end, a middle section and a second end along the length direction; a gate-all-around surrounding the middle section; a source/drain functional portion; and a spacer structure including first and second spacers. The first spacer is between first ends and second ends of adjacent channel layers, and includes a cavity. The second spacer is on a side of the channel layer stacking portion away from the substrate and on both sides of the gate-all-around along the length direction. A dielectric constant of the first spacer is greater than that of the second spacer.