Dielectric Anchor Void Layout for Nanowire Gate Plug Etching
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors is exacerbated by the constraints on lithographic processes, leading to a trade-off between feature dimension and spacing, which complicates the fabrication of integrated circuits, particularly in tri-gate transistors on bulk silicon substrates.
Innovation Solution
The implementation of self-aligned dielectric anchor voids and selective removal of anchors in integrated circuit structures, allowing for reduced aspect ratio gate plugs and improved process control through techniques like plug-last approaches, which facilitate seamless work function metal deposition and reduce void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature dimensions are reduced to increase device density, then device capacity increases, but lithographic process constraints worsen
Solution Approach 1:
The patent segments the gate structure into multiple components: dielectric anchors, gate plugs, and work function metal layers. The dielectric anchors are selectively removed in certain regions to create voids, allowing independent optimization of different gate regions. This segmentation enables the gate structure to accommodate lithographic constraints while maintaining high device density.
Solution Approach 2:
The patent introduces vertical dimensionality by creating dielectric anchor voids beneath the gate structure. This vertical void formation allows the gate plug to be positioned at different heights relative to the channel, effectively adding a z-dimension to the patterning problem. This dimensional change relaxes the lateral lithographic constraints by decoupling gate alignment from complete plug formation.
2Device complexity
If multi-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing complexity decreases, but device performance control worsens
Solution Approach 1:
The patent applies local quality by selectively removing dielectric anchors only in specific regions beneath certain gates. This creates localized voids that improve short channel control in those specific transistor regions while maintaining the overall bulk silicon substrate structure. The selective anchor removal allows performance optimization in critical areas without complicating the entire fabrication process.
3Quantity of substance
If gate plugs with high aspect ratio are formed, then device density increases, but etch process control worsens
Solution Approach 1:
The patent performs preliminary action by forming dielectric anchors before gate plug deposition, then selectively removing these anchors to create voids. This preliminary void formation allows subsequent gate plugs to be formed with lower aspect ratios since the void space provides relief during the etching process. The anchors serve as temporary structures that facilitate easier plug formation.
Solution Approach 2:
The dielectric anchors act as intermediary structures that mediate between the high-density requirement and the etch process control. The anchors are formed, then selectively removed to create voids that serve as intermediaries allowing gate plugs to be formed with relaxed aspect ratio constraints. This intermediary approach decouples the density requirement from the etching difficulty.
Data Source
AI summary
Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.