Segmented Gate Isolation Structure for Gate Fill Window Preservation
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, multi-gate devices face challenges with increased parasitic capacitance between adjacent gate structures, which affects device performance and complicates the formation of satisfactory gate structures due to reduced gate fill windows.
Innovation Solution
A method is introduced to form a gate isolation structure by removing a portion of the dielectric fin to create an isolation trench, allowing for a wider gate isolation structure that directly contacts the gate electrode layers, thereby reducing parasitic capacitance without compromising the gate formation window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the width of gate cut feature or dielectric fin is increased to reduce parasitic capacitance between adjacent gate structures, then parasitic capacitance is reduced, but the gate fill window is reduced making it difficult to form satisfactory gate structures
Solution Approach 1:
The gate isolation structure is divided into two distinct portions: a lower portion that provides parasitic capacitance reduction and an upper portion that maintains gate formation window. This segmentation allows each portion to optimize for its specific function without compromising the other.
Solution Approach 2:
The gate isolation structure transitions from a conventional single-level dielectric fin to a multi-level structure with lower and upper portions at different vertical levels. The lower portion extends between gate structures at a first level, while the upper portion rises to a second level, utilizing vertical dimensionality to simultaneously achieve capacitance reduction and maintain manufacturing window.
2Ease of manufacture
If conventional gate cut features or dielectric fins are used, then gate structures can be formed, but parasitic capacitance between adjacent gate structures remains high
Solution Approach 1:
The lower portion of the gate isolation structure is formed first to establish the foundation for parasitic capacitance reduction. Subsequently, the upper portion is added to complete the isolation structure, ensuring both manufacturing ease and reduced parasitic capacitance are achieved through this sequential preliminary action approach.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.