3D Semiconductor Contact Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The increasing integration of semiconductor devices poses challenges in maintaining high electrical performance and reliability, particularly due to size reduction and the need for improved operating characteristics in semiconductor devices with BackSide Power Delivery Network (BSPDN) structures and three-dimensional channels.
Innovation Solution
A semiconductor device design featuring insulating isolation patterns with voids, channel structures, gate structures, and specific source/drain patterns, along with active and dummy contact structures, reduces parasitic capacitance and enhances electrical connectivity through a double-sided interconnection structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the degree of integration of semiconductor devices is increased, then the functionality and performance are improved, but parasitic capacitance increases and electrical characteristics deteriorate
Solution Approach 1:
The patent introduces a void within the insulating isolation pattern, creating a three-dimensional structure that extends beneath adjacent contact structures. This vertical dimensionality change allows the isolation pattern to electrically isolate contacts without increasing planar area, thereby reducing parasitic capacitance while maintaining high device integration
Solution Approach 2:
The insulating isolation pattern with an integrated void acts as an intermediary structure between adjacent contact structures. It provides electrical isolation between contacts while the void space enables this isolation function without requiring additional lateral spacing, thus reducing parasitic capacitance between neighboring contacts
2Productivity
If the size of planar MOSFETs is reduced, then the integration density is improved, but operating characteristics are limited
Solution Approach 1:
The patent employs three-dimensional channel structures that extend vertically, allowing the transistor channel to utilize the vertical dimension for current flow. This enables higher integration density in the planar direction while maintaining adequate channel dimensions for proper device operation, thus improving both integration density and operating characteristics
3Reliability
If insulating isolation patterns are used to electrically isolate contact structures, then electrical isolation is improved, but parasitic capacitance between contacts increases
Solution Approach 1:
The insulating isolation pattern extends vertically to form a three-dimensional structure with a void inside it, positioned beneath the adjacent contact structure. This vertical extension provides electrical isolation between contacts while the void reduces the capacitance-forming area, thereby achieving both good electrical isolation and reduced parasitic capacitance
Solution Approach 2:
The insulating isolation pattern contains an internal void, creating a porous or hollow structure. This void reduces the effective dielectric material volume between adjacent contacts, thereby reducing parasitic capacitance while the outer walls of the isolation pattern maintain electrical isolation functionality
Data Source
AI summary
A semiconductor device includes insulating isolation patterns each including a void, semiconductor patterns respectively stacked on the insulating isolation patterns, gate structures respectively extending around the semiconductor patterns, first and second source/drain patterns respectively connected to opposing sides of the plurality of semiconductor patterns in a first direction, an active contact structure extending between insulating isolation patterns adjacent to the first source/drain pattern and connected to the first source/drain pattern, a dummy contact structure extending between the insulating isolation patterns adjacent to the second source/drain pattern and electrically isolated from the second source/drain pattern, and an interconnection line on lower surfaces of the insulating isolation patterns, electrically connected to the active contact structure, and electrically isolated from the dummy contact structure.