Vertical Memory Stack Openings With Double Pocket Isolation
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving high memory cell integration and reducing parasitic capacitance in three-dimensional memory devices.
Innovation Solution
The fabrication method involves forming a vertical stack with alternating dielectric and horizontal layers, incorporating cell isolation layers and sacrificial structures, and creating storage openings with a double pocket layer to form data storage elements, using materials like monocrystalline silicon, oxide semiconductors, or two-dimensional materials for enhanced integration and reduced capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three-dimensional structure to increase integration, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
The memory device is divided into multiple independent vertical stacks, each containing separated memory cells. The cell isolation layers segment the conductive structures vertically, electrically isolating adjacent memory cells to reduce parasitic capacitance while maintaining high integration through the stacked configuration.
Solution Approach 2:
Cell isolation layers are introduced as intermediary structures between adjacent memory cells and conductive lines. These isolation layers act as dielectric barriers that prevent direct electrical coupling, thereby reducing parasitic capacitance between neighboring cells while allowing the three-dimensional stacked architecture to maintain high density.
2Manufacturing precision
If complex fabrication processes are used to achieve high integration, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Sacrificial structures are formed in advance before the final memory cell structure is completed. These preliminary structures guide the formation of storage openings and are subsequently removed, simplifying the overall fabrication process by providing a template that ensures precise alignment and positioning of critical components.
Solution Approach 2:
The patent employs three-dimensional vertical stacking to achieve high integration, transitioning from planar two-dimensional layouts. This dimensional change allows multiple memory cells to be packed in a compact volume, improving density while the standardized vertical stack design actually reduces fabrication complexity compared to complex planar interconnections.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E
AI summary
The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating a semiconductor device includes forming a vertical stack in which dielectric layers are alternately stacked with horizontal layer patterns, over a lower structure; forming cell isolation layers that contact side surfaces of the horizontal layer patterns and vertically extend in the vertical stack; forming a sacrificial structure that covers upper surfaces and lower surfaces of the horizontal layer patterns in the vertical stack; forming a hole-shape opening that vertically extends, by etching the sacrificial structure and the cell isolation layers; forming a double pocket layer on a sidewall of the hole-shape opening; forming storage openings, by recessing the horizontal layer patterns and the cell isolation layers using the double pocket layer as a barrier; and forming a data storage element in each of the storage openings.