Necked GAA Nanowire Structure for Short-Channel Control
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern features, leading to a trade-off between critical dimension and spacing.
Innovation Solution
The introduction of necked features in gate-all-around integrated circuit structures, where nanowires or nanoribbons have differentiated vertical thickness, allowing for improved short channel effects and voltage threshold tuning without a complex integration scheme, achieved through processes like epitaxial growth and replacement gate techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase functional unit density, then device capacity increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control and short channel effect suppression at scaled dimensions while maintaining device density
2Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing complexity decreases, but mobility improvement and short channel control are compromised
Solution Approach 1:
The patent introduces necked regions with reduced cross-sectional area at specific locations along the nanowire channel, creating localized variations in electrical properties. This local structural modification enhances gate control over the channel without requiring complete redesign of the substrate or overall device architecture, enabling improved short channel control while maintaining compatibility with bulk silicon fabrication processes
3Manufacturing precision
If lithographic processes are used to pattern features at smaller dimensions, then critical dimension decreases, but spacing between features must increase due to process constraints
Solution Approach 1:
The patent employs self-aligned fabrication techniques where subsequent lithographic steps are automatically positioned relative to previously formed structures. This self-alignment approach eliminates the need for additional spacing between features that would otherwise be required to ensure proper alignment, enabling tighter feature pitch while maintaining manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances short channel control and voltage threshold tuning, improving device performance and reducing manufacturing complexity, enabling higher device densities and lower patterning costs.
Implementation Method 1
Nanowires used to fabricate devices provide improved short channel control
Implementation Method 2
achieved through processes like epitaxial growth and replacement gate techniques
Data Source
AI summary
Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.