Stacked Channel Semiconductor Structure With Self-Aligned Vertical Vias
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration density and improved electrical characteristics, particularly in the manufacturing process of vertical vias, which complicates the manufacturing process and affects device performance.
Innovation Solution
A semiconductor device structure is designed with a self-aligned formation of vertical vias using the etch selectivity of dummy patterns and their liner layers, allowing for reduced manufacturing complexity and improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form vertical vias in semiconductor devices, then the manufacturing process becomes complex and difficult, but integration density and electrical characteristics cannot be sufficiently improved
Solution Approach 1:
The patent applies preliminary action by forming dummy patterns and liner layers on sidewalls of source/drain patterns before forming the vertical vias. These preliminary structures serve as self-aligned masks and liners that guide the via formation process, eliminating the need for complex alignment steps and reducing manufacturing complexity while improving precision
Solution Approach 2:
The dummy patterns and liner layers form a self-aligned system where the via formation process automatically uses the existing sidewall structures as references. This self-service mechanism eliminates the need for separate alignment processes and complex manufacturing steps, simultaneously improving precision and reducing process complexity
2Productivity
If integration density is increased to meet performance requirements, then device functionality improves, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The dummy patterns and liner layers are formed in advance on the sidewalls of source/drain patterns, creating a self-aligned reference system that simplifies subsequent via formation. This preliminary action enables high integration density while maintaining manufacturing ease by eliminating complex alignment procedures
Solution Approach 2:
The self-aligned via formation process uses the existing dummy patterns and liner layers as automatic references, allowing the manufacturing process to self-correct and self-align. This enables increased integration density without proportionally increasing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned formation of vertical vias simplifies the manufacturing process and enhances the electrical performance of semiconductor devices, leading to improved integration density and reliability.
Implementation Method 1
the vertical via may be formed in a self-aligned manner using the etch selectivity of the dummy pattern and the dummy pattern liner layer of the second dummy structure
Data Source
AI summary
Provided is a semiconductor device including: a lower active region extending in a first direction and including a lower channel pattern and a lower source/drain pattern on a side of the lower channel pattern; an upper active region spaced apart from the lower channel pattern in a second direction, extending in the first direction, and including an upper channel pattern and an upper source/drain pattern on a side of the upper channel pattern; a gate electrode surrounding the upper and lower channel patterns, and extending in a third direction; a lower source/drain contact below and connected to the lower source/drain pattern; an upper source/drain contact above and connected to the upper source/drain pattern; a vertical via on one side of the upper source/drain pattern and connected to the lower and upper source/drain contacts; and a first dummy structure on another side of the upper source/drain pattern, the first dummy structure including a first dummy pattern extending in the first direction.