Multi-Gate Nanosheet FET Layout for Dummy Gate Overlay Shift

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Solution Overview

Problem

Existing methods for forming nanosheet field-effect transistors (NS FETs) suffer from inadvertent overlay shifts during patterning of dummy gate stacks, leading to structural defects that degrade device performance.

Innovation Solution

The formation of jog structures, such as bridge structures or protruding portions, over the dummy gate stacks to ensure alignment with fin edges, reducing the formation of epitaxial mushroom defects and preventing electrical shorting by covering the dielectric helmet with these structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If existing methods are used to form dummy gate stacks, then the NS FET structure can be formed, but overlay shifts occur during patterning causing structural defects

Engineering Contradiction:

Improvealignment precision of dummy gate stacksVSAvoiddevice performance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The method performs preliminary patterning of the dummy gate stack with intentional offset from the fin edge, then uses a second patterning step to form the actual gate structure. This preliminary action with built-in offset compensation prevents the overlay shift problem that would otherwise occur during single-step patterning, ensuring both manufacturing precision and device reliability.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If precise alignment is achieved, then structural defects are reduced, but processing complexity increases

Engineering Contradiction:

Improvealignment precision of gate structuresVSAvoidprocessing steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dummy gate stack serves as an intermediary structure that is intentionally misaligned and then corrected in a subsequent step. This intermediary approach allows the use of simpler initial patterning processes while achieving precise final alignment, reducing the need for complex single-step alignment procedures.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12501658B2Multi-gate field-effect transistors and methods of forming the same

Publication Date: 2025.12.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure includes a fin extending from a substrate and oriented lengthwise in a first direction, where the fin includes a stack of semiconductor layers, an isolation feature disposed over the substrate and oriented lengthwise in a second direction perpendicular to the first direction, where the isolation feature is disposed adjacent to the fin, and a metal gate structure having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers. Furthermore, a sidewall of the bottom portion of the metal gate structure is defined by a sidewall of the isolation feature, and the top portion of the metal gate structure laterally extends over a top surface of the isolation feature.