Differentiated Nanowire Stacks for SRAM Vmin and Metal Fill
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern features, leading to a trade-off between critical dimension and spacing.
Innovation Solution
Implementing differentiated channel sizing in integrated circuit structures by varying the number of nanowires or fin heights in memory and logic regions, and using a 'plug-last' approach for metal gate cuts to alleviate space constraints and improve metal fill capabilities, ensuring a seamless work function metal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down below 10 nanometer node, then increased density of functional units is achieved, but maintaining mobility improvement and short channel control becomes difficult
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control and short channel effect suppression at scaled dimensions while maintaining high device density.
Solution Approach 2:
The patent employs composite material structures including semiconductor-sacrificial material stacks (e.g., Si/SiGe alternating layers) that are selectively removed to form nanowires. This composite approach enables precise control of nanowire formation, crystalline orientation, and material properties, achieving both high density and reliable device performance at sub-10nm nodes.
2Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then lower cost and less complicated fabrication process are achieved, but mobility improvement and short channel control are compromised
Solution Approach 1:
The patent segments the channel region into multiple independent nanowires stacked vertically, each surrounded by its own gate structure. This segmentation is achieved by selectively removing sacrificial material layers, creating discrete nanowire channels that provide superior gate control compared to conventional bulk silicon structures, while still using bulk silicon as the starting substrate.
Solution Approach 2:
The gate structure is nested around the nanowire channel in a gate-all-around configuration, with the gate wrapping completely around the channel from top to bottom and all sidewalls. This nested geometry provides maximum electrostatic control and mobility enhancement, achieving performance benefits typically associated with complex processes while maintaining compatibility with bulk silicon fabrication.
3Manufacturing precision
If lithographic processes are used to pattern features at smallest dimensions, then critical dimension is reduced, but spacing between features increases
Solution Approach 1:
The patent utilizes vertical stacking of multiple nanowires in the third dimension to achieve high device density without increasing lateral spacing. By forming nanowires at different vertical levels and providing gate-all-around control, the design achieves fine effective channel dimensions while maintaining adequate lithographic spacing, effectively trading vertical for lateral space.
Data Source
AI summary
Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.