Backside Wordline Via Layout for Faster SRAM Signal Routing
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high reliability, high speed, and multifunctionality due to increasing complexity and integration, necessitating improved structural designs.
Innovation Solution
A semiconductor device with a substrate having opposite surfaces featuring front and back wiring patterns connected by through vias, along with specific cell and cell array configurations, including latches, pass transistors, and shared contacts, enhances performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the structure within semiconductor devices becomes increasingly complex and highly integrated to meet demands for high reliability, high speed, and multifunctionality, then device performance is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent utilizes back-side wiring patterns and through-substrate vias to route wordlines from the back surface of the substrate to the front surface, effectively adding a vertical dimension to the wiring architecture. This allows complex front-side circuits to be simplified by distributing wiring functions across both surfaces of the substrate, thereby improving reliability without proportionally increasing manufacturing complexity
2Speed
If through vias are used to connect front and back wiring patterns, then signal transmission is optimized and device speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The wordline is segmented into multiple portions: a first wiring pattern on the front surface, a second wiring pattern on the back surface, and through-substrate vias connecting them. This segmentation allows each component to be optimized independently - the vias can be precisely aligned during manufacturing while the wiring patterns can be designed to compensate for minor variations, thereby achieving high-speed signal transmission without excessively stringent precision requirements
3Adaptability or versatility
If more wiring patterns and interconnections are added to achieve multifunctionality, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The back-side wiring patterns and through-substrate vias create a universal interconnection architecture that can support multiple functions. The same back-side wordline structure can serve different memory cells and support various operational modes (read, write, refresh), thereby achieving multifunctionality without proportionally increasing manufacturing complexity since the basic structural elements remain the same
Data Source
AI summary
A semiconductor device includes: a substrate having first and second surfaces; a wordline including a front wiring pattern on the first surface and a back wiring pattern on the second surface; a bitline and a complementary bitline on the substrate; and first and second cells on the substrate. The first cell includes: a latch circuit with first and second inverters; a first pass transistor connected between an output node of the first inverter and the bitline; and a second pass transistor connected between an output node of the second inverter and the complementary bitline. The second cell includes a through via penetrating the substrate and connecting the front wiring pattern and the back wiring pattern.