Subfin Gate Structure Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
As integrated circuits scale downward in size, parasitic effects from semiconductor subfins beneath semiconductor regions form parasitic junctions and capacitors, reducing transistor switching speed and degrading performance.
Innovation Solution
A sacrificial material layer is deposited along the bottom of a gate trench to prevent the gate structure from forming around the sides of subfins, followed by removing the semiconductor material of the subfins from the backside and filling the resulting cavities with dielectric materials, ensuring the gate structure does not extend below the top surface of dielectric subregions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure is formed to extend around the sides of subfins, then the transistor control is improved, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The patent removes the harmful subfin structures from beneath the semiconductor regions, extracting the source of parasitic capacitance while maintaining the beneficial gate control through alternative structural arrangements
Solution Approach 2:
The patent converts the potentially harmful gate-subfin junctions into beneficial configurations by preventing gate structure formation around subfins, thereby eliminating parasitic effects while preserving transistor control through the main gate structure
2Productivity
If integrated circuits are scaled downward in size, then device density is improved, but parasitic effects from subfins increase and degrade performance
Solution Approach 1:
The patent extracts and removes the harmful subfin structures that generate parasitic effects, allowing high-density integration without the performance degradation caused by parasitic capacitance and junction effects
Solution Approach 2:
The patent applies different structural treatments to different regions: subfins are removed beneath semiconductor regions to eliminate parasitic effects, while the main fin structures are retained to provide transistor channel regions for high-density device operation
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C~2D
AI summary
Techniques are provided herein to form semiconductor devices with gate structures that do not extend below a top surface of dielectric subregions. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the fin of semiconductor material includes a subfin adjacent to a dielectric fill. A sacrificial material layer is deposited before the formation of the gate structure to prevent the gate structure from forming along the sides of the subfin. This sacrificial layer may then be removed from the backside of the structure along with the semiconductor material of the subfin. The subfin area may be replaced with one or more dielectric materials formed on the backside. As a result, the device performance is improved by lowering the parasitic capacitance caused by having the gate structure on either side of the dielectric structure replacing the subfin region.