Source/Drain Spacer and Etch Stop Layout for Tight-Pitch Etching
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Solution Overview
Problem
The increased integration of semiconductor devices leads to complex spacer structures during etching, which can result in inadequate thickness and poor shaping of device elements.
Innovation Solution
The implementation of a semiconductor device design that includes multiple layers of spacers and etch stop patterns, allowing for precise etching by using sacrificial gate spacers made of silicon nitride that are not removed during cleansing processes, ensuring accurate shaping of source/drain layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the spacer structure is made complex with multiple layers to accommodate increased integration, then the degree of integration is improved, but the thickness of the spacer structure increases and etching performance deteriorates
Solution Approach 1:
The spacer structure is divided into multiple discrete layers including a first spacer layer, a second spacer layer, and an etch stop layer. Each layer serves a specific function: the first and second spacer layers provide spacing functionality, while the etch stop layer prevents excessive etching. This segmentation allows the structure to maintain both the complexity needed for high integration and the controlled thickness required for proper etching performance.
2Manufacturing precision
If the spacer structure thickness is increased to maintain etching margin, then etching performance is improved, but the degree of integration deteriorates due to increased spacing requirements
Solution Approach 1:
Instead of using a single thick spacer layer, the structure employs multiple thinner spacer layers separated by an etch stop layer. This segmentation distributes the total thickness across multiple layers, maintaining the necessary etching margin while allowing better control over the vertical space consumption, thus supporting higher degree of integration.
Solution Approach 2:
The etch stop layer acts as an intermediary between the first and second spacer layers. It provides a controlled barrier that prevents the etching process from penetrating too deeply, thereby maintaining etching margin without requiring excessive total spacer thickness. This intermediary layer enables precise control over the etching depth while preserving space for high integration.
3Manufacturing precision
If simpler spacer structures are used to maintain etching performance, then etching performance is improved, but the ability to accommodate increased integration deteriorates
Solution Approach 1:
The spacer structure is segmented into functional layers that can be independently optimized. The first spacer layer, second spacer layer, and etch stop layer can be designed with specific thicknesses and material properties to simultaneously achieve good etching performance and support the complex routing requirements of high integration circuits.
Solution Approach 2:
The multi-layer spacer structure serves multiple functions: providing electrical isolation, maintaining mechanical spacing, controlling etching depth, and supporting complex interconnect routing. This multi-functionality allows a single structure to address both etching performance requirements and integration capability needs.
Data Source
AI summary
A semiconductor device includes first and second channels, first and second gate structures, first and second source/drain layers, first and second fin spacers, and first and second etch stop patterns. The first channels are disposed vertically on a first region of a substrate. The second channels are disposed vertically on a second region of the substrate. The first gate structure is formed on the first region and covers the first channels. The second gate structure is formed on the second region and covers the second channels. The first and second source/drain layers contact the first and second channels, respectively. The first and second fin spacers contact sidewalls and upper surfaces of the first and second source/drain layers, respectively. The first and second etch stop patterns are formed on the first and second fin spacers, respectively, and do not contact the first and second source/drain layers, respectively.


