Dielectric Wall Stress Layout for Forksheet Channel Mobility

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Solution Overview

Problem

Existing semiconductor devices, particularly forksheet transistors, face limitations in applying channel stress effectively in both the channel-width and channel-length directions, which affects carrier mobility and device performance.

Innovation Solution

The introduction of a dielectric wall formed of specific materials that can exert compressive or tensile stress on the channel structure in the channel-width direction, depending on the polarity type and surface orientation of the nanosheet transistors, allowing for enhanced carrier mobility by applying stress in both the 1st and 2nd directions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dielectric wall is introduced to apply channel stress in the channel-width direction, then carrier mobility is enhanced, but device complexity increases

Engineering Contradiction:
Improvecarrier mobilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is segmented into two separate channel structures (first and second channel structures) positioned on opposite sides of the dielectric wall. This segmentation allows independent stress application to each channel while maintaining a shared isolation structure, thereby enhancing carrier mobility in both channels without proportionally increasing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dielectric wall serves multiple functions simultaneously: it acts as an isolation structure separating the two channel structures, applies channel stress in the channel-width direction to enhance carrier mobility, and provides mechanical support for the nanosheet channel layers. This multi-functionality resolves the contradiction by delivering performance benefits without proportional complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If stress is applied in both channel-length and channel-width directions, then device performance is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedevice performanceVSAvoidstress application precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Different stress conditions are applied to different regions of the device. The source/drain structures apply stress in the channel-length direction to specific localized regions, while the dielectric wall applies stress in the channel-width direction. This local quality approach allows optimized stress distribution without requiring uniform precision across the entire device structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The stress application is made dynamic and adaptable through material selection. The dielectric wall is formed from materials with specific stress characteristics (compressive or tensile) that can be selected based on the desired stress direction and magnitude. This dynamic approach allows manufacturing processes to adjust stress conditions without requiring extreme precision.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly increases carrier mobility in forksheet transistors, improving device performance by optimizing stress application based on transistor polarity and surface orientation, thereby enhancing overall semiconductor device efficiency.

Implementation Method 1

a dielectric wall formed of a material that can exert a compressive stress or a tensile stress on a channel structure in a channel-width direction

Methodology Applied
Scientific EffectStress:

Data Source

PatentUS20250380504A1Semiconductor device including dielectric wall applying channel stress to channel structure
Publication Date: 2025.12.11 SAMSUNG ELECTRONICS CO LTD
  • US20250380504A1 patent drawing
  • US20250380504A1 patent drawing
  • US20250380504A1 patent drawing

AI summary

Provided is a semiconductor device which includes: a 1st channel structure extended in a 1st direction; a 1st source/drain pattern on the 1st channel structure; a 2nd channel structure extended in the 1st direction at a side of the 1st channel structure in a 2nd direction intersecting the 1st direction; a 2nd source/drain pattern on the 2nd channel structure; and a 1st dielectric wall between the 1st channel structure and the 2nd channel structure, wherein the 1st source/drain pattern and the 2nd source/drain pattern are each of n-type, and a top surface and a side surface of each of the 1st channel structure and the 2nd channel structure is in a (110) orientation and in a (100) orientation, respectively.