Fin-Structure SOI Transistor Layout for Floating Body Suppression

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Solution Overview

Problem

Semiconductor devices with fin-type transistors on silicon-on-insulator (SOI) substrates suffer from floating body effects, leading to characteristic variations such as threshold voltage fluctuations due to accumulated electric charge, and attempts to mitigate this by connecting the channel to the substrate reduce the effectiveness of the SOI structure.

Innovation Solution

A transistor design with a fin structure that includes a channel layer connected to a substrate via a semiconductor layer, a source and drain layer separated by insulating layers, and a gate electrode with portions facing the semiconductor layer, allowing for electrical isolation and connection to the substrate to manage floating body effects without losing the advantages of the SOI structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electrical conduction is made between the channel and the substrate to eliminate the floating body effect, then the floating body effect is suppressed, but the advantage of the SOI structure is lost due to reduced potential change in the channel region

Engineering Contradiction:
Improvefloating body effect suppressionVSAvoidpotential change in channel region
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The gate electrode is divided into two portions: a first portion disposed over the channel layer and a second portion disposed between the substrate and the channel layer. This segmentation allows the first portion to control the channel potential for high transconductance while the second portion provides electrical connection to the substrate to suppress floating body effects, thereby resolving the contradiction between these two requirements.

Inventive Principle:
Principle #1Segmentation

2Power

If the channel is electrically isolated from the substrate to maintain SOI structure advantages, then the potential change in the channel region is enhanced, but the floating body effect occurs causing characteristic variations

Engineering Contradiction:
Improvepotential change in channel regionVSAvoidcharacteristic variation
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The gate electrode is segmented into two portions that perform different functions: the first portion over the channel layer provides gate control for high potential change, while the second portion between the substrate and channel layer provides electrical connection to suppress floating body effects and characteristic variations, thus resolving the contradiction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second portion of the gate electrode acts as an intermediary element that provides a controlled electrical connection path between the channel and substrate. This intermediary structure allows the channel to maintain electrical isolation for SOI advantages while still providing a controlled path to suppress floating body effects through the gate electrode's second portion.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12495608B2Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2025.12.09 UNITED SEMICON JAPAN CO LTD
  • US12495608B2 patent drawing
  • US12495608B2 patent drawing
  • US12495608B2 patent drawing

AI summary

A semiconductor device having a transistor with fin structure includes a channel layer that is disposed over a substrate and is connected to the substrate via a semiconductor layer, a source layer that is disposed on a first side surface of the channel layer over the substrate and is separated from the substrate via a first insulating layer, a drain layer that is disposed on a second side surface of the channel layer opposite to the first side surface over the substrate and is separated from the substrate via a second insulating layer, and a gate electrode including a first portion disposed over the channel layer and a second portion which is disposed between the substrate and the channel layer and whose third side surface or fourth side surface faces the semiconductor layer.