Semiconductor Channel Separation Structure for Parasitic Capacitance Control
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical and reliability characteristics.
Innovation Solution
The semiconductor device incorporates specific structural features such as active and channel patterns, separation patterns with distinct body and head portions, and inner insulating patterns with varying widths, along with gate electrodes and insulating layers to enhance electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then the pattern size and design rule are reduced, but the operational properties of the semiconductor device deteriorate
Solution Approach 1:
The patent applies local quality by providing different width portions of the inner insulating pattern at different locations. The first width portion (between channel patterns and separation pattern) has a different width than the second width portion (between gate electrode and separation pattern), allowing optimized electrical characteristics at each location while maintaining overall device scaling
Solution Approach 2:
The inner insulating pattern is segmented into multiple width portions with different dimensions. This segmentation allows the patent to address different electrical issues (parasitic capacitance near channels, fixed charge near gate) with appropriately sized insulating regions, thereby maintaining operational properties despite overall device scaling
2Device complexity
If the inner insulating pattern has uniform width, then the structure is simple, but parasitic capacitance and fixed charge effects cannot be effectively prevented
Solution Approach 1:
The patent implements local quality by varying the width of the inner insulating pattern at different positions. The first width portion is positioned where parasitic capacitance needs to be minimized, while the second width portion addresses fixed charge effects near the gate electrode, optimizing electrical characteristics without excessive complexity
Data Source
AI summary
A semiconductor device may include an active pattern on a substrate, a first channel pattern and a second channel pattern provided on the active pattern and spaced apart from each other, a separation pattern between the first and second channel patterns, the separation pattern including a body portion and a head portion on the body portion, a gate electrode on the first and second channel patterns, and an inner insulating pattern on a side surface of the body portion. The inner insulating pattern may include a first portion between the first channel pattern and the separation pattern and between the second channel pattern and the separation pattern and a second portion between the gate electrode and the separation pattern. A width of the first portion may be larger than a width of the second portion.