SiGe FinFET Source/Drain Barrier Structure for Reduced Phosphorous Diffusion
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Solution Overview
Problem
As semiconductor devices shrink to nanometer technology nodes, the use of Ge or SiGe as channel regions in FinFETs and GAA FETs leads to high phosphorous diffusion, degrading device performance due to increased Ioff, lower electron mobility, greater dielectric leakage, and reduced reliability.
Innovation Solution
Incorporation of a diffusion barrier layer between the epitaxial semiconductor layer and the source/drain region to suppress impurity diffusion, using silicon-based or silicon germanium-based materials with low phosphorous diffusion coefficients, and employing multiple-layer barrier semiconductor structures to manage lattice mismatch and reduce interface states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Ge or SiGe is used as channel region material, then device performance (electron mobility) is improved, but phosphorous diffusion increases leading to degraded device characteristics
Solution Approach 1:
A diffusion barrier layer comprising Si or SiGe is introduced between the Ge/SiGe channel region and the phosphorous-doped epitaxial layer. This intermediary layer acts as a mediator that allows the high-electron-mobility Ge/SiGe channel to maintain its performance while blocking phosphorous atoms from diffusing into the channel region, thus resolving the contradiction between device performance and phosphorous diffusion control
2Object-generated harmful factors
If diffusion barrier layer is introduced, then phosphorous diffusion is reduced, but device structure complexity increases
Solution Approach 1:
The diffusion barrier layer is applied locally only at the critical interface between the epitaxial layer and the channel region, rather than throughout the entire device structure. This localized approach provides effective phosphorous diffusion control precisely where needed while minimizing the overall structural complexity and maintaining ease of fabrication
3Stability of the object's composition
If multiple-layer barrier structures are used, then lattice mismatch and interface states are managed, but manufacturing complexity increases
Solution Approach 1:
The barrier layer composition is optimized by adjusting the SiGe ratio parameter to match the lattice constants of adjacent layers. By carefully controlling the geometric parameter (composition ratio) of the barrier layer, the structure achieves effective lattice mismatch management and reduced interface states while maintaining a relatively simple single-layer or few-layer configuration that is ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The diffusion barrier layer effectively reduces phosphorous diffusion, maintaining device performance by minimizing Ioff, enhancing electron mobility, reducing dielectric leakage, and improving reliability in FinFETs and GAA FETs.
Implementation Method 1
Incorporation of a diffusion barrier layer between the epitaxial semiconductor layer and the source/drain region to suppress impurity diffusion, using silicon-based or silicon germanium-based materials with low phosphorous diffusion coefficients
Data Source
AI summary
In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of SixGe1-x, where 0≤x≤0.3, the first semiconductor layer is made of SiyGe1-y, where 0.45≤y≤1.0, and the second semiconductor layer is made of SizGe1-z, where 0≤z≤0.3.