Offset Channel Structure for Dense 3D Transistor Contacts
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Solution Overview
Problem
The challenge of increasing transistor density in integrated circuits with limited space is addressed by developing semiconductor devices with multi-stack structures, where transistors are formed in a lower and upper stack, but existing designs face challenges in optimizing contact structure space within a high-density footprint.
Innovation Solution
The semiconductor device incorporates a lower and upper transistor structure with horizontally offset channel layers, allowing for non-overlapping portions in the vertical direction and enabling efficient contact structure placement without horizontal interference, thereby reducing pitch and improving integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are stacked vertically to increase density, then transistor density is improved, but contact structure placement becomes more difficult
Solution Approach 1:
The patent applies dimensional change by offsetting the upper channel structure horizontally relative to the lower channel structure in the vertical direction. This creates non-overlapping regions that provide vertical clearance for contact structures to access the source/drain regions without horizontal interference, thus resolving the conflict between high-density stacking and contact placement feasibility.
2Ease of manufacture
If channel structures are aligned vertically, then manufacturing is simpler, but contact structure space is reduced
Solution Approach 1:
The invention transitions from two-dimensional vertical alignment to three-dimensional offset alignment. By introducing horizontal offset between upper and lower channel structures, the patent creates additional vertical clearance space for contact structures while maintaining relatively simple manufacturing processes through standard lithography and etching techniques.
3Length of stationary object
If upper and lower channel structures overlap completely, then vertical space is optimized, but contact structure access is blocked
Solution Approach 1:
The patent segments the channel structures into offset upper and lower portions, creating distinct horizontal zones. This segmentation provides dedicated vertical access paths for contact structures to reach the source/drain regions without being blocked by overlapping channel structures, while still maintaining efficient vertical space utilization through partial overlap.
Data Source
AI summary
A semiconductor device includes: a lower transistor including a lower channel structure and a lower source/drain structure on the lower channel structure; and an upper transistor above the lower transistor, the upper transistor including an upper channel structure and an upper source/drain structure on the upper channel structure, wherein a portion of the upper channel structure overlaps the lower channel structure in a vertical direction, and another portion of the upper channel structure does not overlap the lower channel structure in the vertical direction.