3D Computation Array for Parallel Multi-Channel CNN Processing
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Solution Overview
Problem
Convolutional computations in deep convolutional neural networks (CNNs) are inefficient due to high data transfer requirements, leading to increased time and energy consumption, and existing processing element arrays do not support simultaneous computations of multi-channel input feature maps, affecting throughput.
Innovation Solution
A computation array is arranged in a 3D architecture with computation units organized along width, height, and channel directions, allowing parallel loading of feature map and weight parameters based on the channel direction, reducing data transfer and improving energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing PE array uses time-sharing to import input feature maps of different channels, then the device complexity is reduced, but the productivity is decreased due to sequential processing
Solution Approach 1:
The patent transitions from a 2D PE array to a 3D PE array by adding a channel dimension. The computation units are arranged in three directions: width direction, height direction, and channel direction. This dimensional extension allows simultaneous processing of multi-channel input feature maps in parallel, thereby improving throughput without using time-sharing methods.
2Manufacturing precision
If convolutional computations require a lot of data transfer, then the manufacturing precision is maintained, but the use of energy increases and computation time is extended
Solution Approach 1:
The patent implements on-chip memory nested within the 3D PE array structure. The memory is integrated into the computation array, allowing computation units to directly access weight parameters and input feature map data stored in the nested memory structure. This eliminates the need for frequent off-chip data transfers, reducing energy consumption while maintaining computation accuracy.
3Manufacturing precision
If convolutional computations require a lot of data transfer, then the manufacturing precision is maintained, but the loss of time increases
Solution Approach 1:
The patent loads weight parameters and input feature map data into the on-chip memory in advance before computation begins. The 3D PE array structure allows parallel preloading of data for multiple channels simultaneously. This preliminary action eliminates waiting time during computation and avoids repeated data transfers, thereby reducing total computation time while maintaining accuracy.
4Device complexity
If existing PE array processes multi-channel data sequentially, then the device complexity is reduced, but the loss of time increases
Solution Approach 1:
The patent adds a channel dimension to the PE array, creating a 3D structure where computation units are arranged along width, height, and channel directions. This allows parallel processing of multi-channel data in the channel direction, eliminating sequential processing delays and reducing total computation time while managing complexity through structured array organization.
Solution Approach 2:
The patent merges the processing of multiple channels into a single 3D PE array structure. Computation units for different channels are integrated and can operate simultaneously on the same input feature map data. This merging allows parallel execution of convolutional computations across channels, reducing computation time compared to sequential processing.
Data Source
AI summary
The disclosure describes a computation array, a computation method, an apparatus and a device, where the computation array includes a plurality of computation units arranged in an array along a first direction, a second direction and a third direction. The first direction corresponds to a width direction of feature map data input into the computation array, the second direction corresponds to a height direction of the feature map data input to the computation array, and the third direction corresponds to a channel direction of the feature map data input to the computation array.