3D Vertical Channel Layout With Sacrificial Isolation Gaps
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Solution Overview
Problem
The challenge in microelectronic device fabrication is to overcome scaling limitations in two-dimensional circuits by transitioning to three-dimensional semiconductor structures, where transistors are stacked vertically, while managing wafer stress and overlay issues that arise from stacking.
Innovation Solution
The method involves forming vertically stacked channel structures with sacrificial epitaxial layers, accessing and removing these layers through openings to create air gaps or fill with dielectric material, which provides isolation and enhances device performance, allowing for compact 3D device layouts and mitigating wafer stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are stacked vertically to increase transistor density, then productivity increases, but wafer stress and overlay issues worsen
Solution Approach 1:
The patent divides the vertical channel structure into multiple segments separated by sacrificial layers. These sacrificial layers are removed to create isolated vertical channels, segmenting the continuous structure into discrete units. This segmentation reduces cumulative wafer stress that would accumulate in a continuous stacked structure while maintaining high transistor density through vertical arrangement.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary elements between vertically stacked channels. These sacrificial layers act as mediators that are temporarily present during fabrication to enable precise patterning and alignment, then removed to create isolation. This intermediary approach solves the overlay alignment problem by providing reference structures during the stacking process.
2Area of stationary object
If vertically stacked channel structures are formed to overcome scaling limitations, then area utilization improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers and defining vertical channel positions before actual channel formation. The sacrificial layers are epitaxially grown and patterned in advance to establish the spatial framework for subsequent channel deposition. This preliminary structuring simplifies the overall manufacturing process by pre-defining the complex 3D geometry, making the vertical stacking process more manageable despite the increased device complexity.
Solution Approach 2:
The patent transitions from two-dimensional planar device layout to three-dimensional vertical stacking by introducing the vertical dimension. Multiple channels are stacked vertically through the thickness of the substrate, utilizing the z-dimension to increase transistor density without increasing the planar footprint. This dimensional transition allows area utilization to improve while the sacrificial layer methodology manages the resulting manufacturing complexity.
3Reliability
If sacrificial layers are removed to create air gaps for isolation, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in the sacrificial layer material properties to achieve precise isolation. The sacrificial layer is made of a material with specific etch selectivity that allows it to be removed selectively without affecting surrounding structures. By changing the material parameters (etch rate, selectivity ratio) of the sacrificial layer relative to other layers, the patent achieves high precision isolation with air gaps while managing manufacturing precision requirements through material selection rather than purely geometric control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased transistor density, improved isolation, and high-performance 3D device performance by creating air gaps or dielectric-filled isolation between vertical channel structures, addressing the limitations of 2D circuits and wafer stress challenges.
Implementation Method 1
The sacrificial layer can be removed by isotropic etching
Implementation Method 2
The sacrificial layer can be removed by wet etching
Implementation Method 3
the lower and upper vertical channel structures can be epitaxially grown on the substrate
Implementation Method 4
the sacrificial layer can be of a sacrificial epitaxial material and is epitaxially grown from the lower vertical channel structure
Data Source
AI summary
Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure. The method can further include forming a vertical opening in the layer stack and removing the sacrificial layer through the vertical opening to separate the lower and upper vertical channel structures.