3D Chip Clock Distribution Grid for Synchronized Signal Arrival
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Solution Overview
Problem
In three-dimensional integrated circuit (3D-IC) and chip-on-wafer-on-substrate (CoWoS) technologies, unsynchronized clock signals between stacked semiconductor chips can lead to communication errors during high-speed data transmission, particularly at rates of 4-32 Gbps.
Innovation Solution
Implementing a semiconductor chip as the source of clock signals for other chips in the stack, using a phase lock loop (PLL) to generate synchronized clock signals, and employing a clock signal distribution tree with gating circuits and grids to ensure simultaneous signal arrival across the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each semiconductor chip generates its own clock signal independently, then each chip operates autonomously, but communication errors occur due to unsynchronized clock signals during high-speed data transmission
Solution Approach 1:
The patent introduces a clock signal distribution tree as an intermediary structure that receives a reference clock signal and distributes synchronized clock signals to multiple semiconductor chips. This mediator ensures all chips operate with synchronized clocks while maintaining autonomous functionality, resolving the contradiction between communication reliability and device complexity.
Solution Approach 2:
The clock distribution system is segmented into a reference clock source, a distribution tree with multiple branches, and individual chip clock inputs. This segmentation allows the system to maintain a single authoritative clock source while providing dedicated clock signals to each chip, ensuring synchronization without requiring complex inter-chip coordination.
2Reliability
If clock signals are distributed across multiple chips without synchronization, then device complexity is reduced, but data transmission reliability deteriorates at high speeds
Solution Approach 1:
The system performs preliminary synchronization by establishing a reference clock signal before data transmission begins. The clock distribution tree pre-distributes synchronized clock signals to all chips, ensuring they are ready and aligned before high-speed data transmission occurs, thereby guaranteeing transmission reliability.
Solution Approach 2:
The patent implements a feedback mechanism where chip select signals are synchronized with the clock distribution tree, ensuring that data transmission only occurs when the receiving chip is properly selected and synchronized. This feedback control prevents communication errors during high-speed transmission.
Data Source
AI summary
A system includes a plurality of stacked semiconductor chips, one of which includes a distribution network, an output clock signal generator, a clock signal grid, a conductive layer. The distribution network generates a plurality of input clock signals and a plurality of first output clock signals, each corresponding to the input clock signal. The output clock signal generator generates a plurality of second output clock signals, each corresponding to the first output clock signal. The clock signal grid interconnects inputs or outputs of the distribution network and facilitates the substantially simultaneous arrival of the first output clock signals at the output clock signal generator. The conductive layer is formed over a surface of the first semiconductor chip and is connected to the clock signal grid.