Logic Circuits Coupling/Interface Using Field-Effect Transistors TRIZ Cases
- 3D Chip Clock Distribution Grid for Synchronized Signal Arrival
A PLL-driven clock distribution tree and grid synchronize stacked chips to prevent high-speed 3D-IC communication errors.
- Non-Volatile Memory Cell Coupling Gate for Low-Power Programming
A coupling gate raises floating-gate voltage for more efficient programming while cutting the high program current of conventional non-volatile memory cells.
- Cascoded Power Switch Timing for DC-DC Cross-Conduction Protection
Voltage-monitored cascoded switches sequence HS and LS turn-off timing to limit inductive voltage stress and prevent cross conductance in DC-DC converters.