Non-Volatile Memory Cell Coupling Gate for Low-Power Programming
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Solution Overview
Problem
Conventional erasable programmable non-volatile memory cells with N-type transistors face high power consumption and low programming efficiency due to high program currents and low induced coupled voltage on the floating gate, making it difficult to increase programming efficiency.
Innovation Solution
The memory cell design includes a p-type well region with n-type doped regions and multiple gate structures, a protecting layer, and a coupling gate structure that enhances programming efficiency by using higher coupling voltages and additional capacitors to manage electron injection and ejection efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high program voltage is applied to achieve electron injection, then programming function is achieved, but power consumption increases due to large program current
Solution Approach 1:
The patent introduces a coupling gate as an intermediary element that mediates the electron injection process. By applying voltage to the coupling gate, electrons are injected into the floating gate through capacitive coupling rather than direct high-current flow, significantly reducing power consumption while achieving the same programming effect
Solution Approach 2:
The patent replaces the conventional direct current-based electron injection mechanism with a voltage-based capacitive coupling mechanism. This substitution changes the fundamental physics from resistive current flow to electric field-induced charge transfer, eliminating the need for large program currents
2Reliability
If conventional erase capacitor arrangement is used, then erase function is achieved, but induced coupled voltage on floating gate is low reducing programming efficiency
Solution Approach 1:
The patent adds a new dimensional element (the coupling gate) to the conventional two-terminal erase capacitor structure. This creates an additional voltage control dimension that enables independent optimization of erase and program operations, allowing high coupled voltage for programming while maintaining erase functionality
Solution Approach 2:
The patent segments the gate structure into multiple independent controllable elements (word line, coupling gate, and floating gate). This segmentation allows independent voltage control of each element, enabling the coupling gate to provide high voltage for efficient programming while the erase capacitor maintains its erase function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces power consumption and enhances programming efficiency by optimizing electron injection and ejection processes, allowing for more precise control over storage states.
Implementation Method 1
When the program current Ip flows through a channel region of the floating gate transistor MF, a channel hot electron injection effect is generated. Due to the channel hot electron injection effect, the hot electrons are injected from the channel region of the floating gate transistor MF into the floating gate GF of the floating gate transistor MF.
Implementation Method 2
When the erase action is performed and proper bias voltages are provided, the electrons stored in the floating gate GF of the floating gate transistor MF are ejected to the erase line EL through the erase capacitor CE.
Data Source
AI summary
A non-volatile memory cell includes a p-type well region, a first n-type doped region, a second n-type doped region, a first gate structure, a second gate structure, a third gate structure and a protecting layer. The first n-type doped region and the second n-type doped region are formed under a surface of the p-type well region. The first gate structure and the second gate structure are formed over the surface of the p-type well region and arranged between the first n-type doped region and the second n-type doped region. A first part of a first gate layer of the first gate structure and the second gate structure are covered by the protecting layer. The third gate structure is formed over the surface of the p-type well region and arranged between the first gate structure and the second gate structure.