3D Chip Stack Inter-Stratum Connectivity Verification
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Solution Overview
Problem
In 3D stacked integrated circuits, existing verification methods fail to ensure that interface signals, clocks, or powers are not unintentionally shorted or left unconnected between strata, leading to connectivity issues due to misalignment of terminal pins and lack of intermediate wires.
Innovation Solution
A method involving 2D layout versus schematic verification on each stratum to pre-ensure the absence of shorts between 3D elements and checking inter-stratum interconnectivity between adjacent pairs, using active, mechanical, and dummy 3D elements to ensure robust connectivity in 3D chip stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-chip LVS and methodology verification tools are used on each stratum individually, then each chip can pass its own verification checks, but interface signals, clocks, or powers can be unintentionally shorted or left unconnected when chips are assembled into a 3D stack
Solution Approach 1:
The verification process is segmented into two distinct phases: (1) conventional single-chip LVS and methodology verification for each stratum individually, and (2) a new 3D-specific inter-stratum connectivity verification step that checks for shorts and opens between adjacent strata. This segmentation allows existing verification tools to be reused while adding targeted 3D connectivity checks.
Solution Approach 2:
The invention performs preliminary 3D-specific verification checks on each stratum before the actual 3D stacking assembly. The verification process checks for potential shorts and opens in inter-stratum connections in advance, allowing design corrections to be made before manufacturing and assembly, thereby preventing connectivity failures in the final 3D stack.
2Adaptability or versatility
If terminal pins from two face-to-face or face-to-back strata are not physically aligned, then connectivity can be achieved through design flexibility, but intermediate wires cannot be used to connect misaligned pins in 3D assemblies
Solution Approach 1:
The invention extends traditional 2D layout verification into the third dimension by performing 3D-specific LVS that accounts for vertical stacking geometry. The verification process checks terminal pin alignment across multiple strata in the vertical dimension, ensuring that pins from adjacent strata are properly aligned for direct connection without requiring intermediate wires that cannot be implemented in 3D stacking.
3Reliability
If 3D-specific LVS and inter-stratum connectivity checks are performed, then connectivity robustness is improved, but verification time and computational resources increase
Solution Approach 1:
The 3D-specific LVS and inter-stratum connectivity verification are performed preliminarily during the design phase on virtual models of the 3D stack, before actual manufacturing and assembly. This early verification prevents costly redesigns and manufacturing defects, reducing overall development time despite the additional computational effort required for 3D verification.
Data Source
AI summary
There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.