Solid-State Devices TRIZ Cases

A photosensitive element manufacturing method deposits a second conductive layer, a photosensitive material layer, and a first top electrode material layer on a substrate.

A buffer chip swaps signals via a swap enable signal to resolve speed versus reliability trade-offs in high-speed storage devices.

Recesses in the monocrystalline substrate create uneven surfaces that enhance light scattering and electrical insulation between stacks.

A solventless epoxy encapsulating composition cures via photopolymerization to form a protective sealing layer on organic electronic devices.

Segmented etching aligns metal vias with 3D NAND control gates, preventing damage during fabrication.

Insulating layers separate p-doped hole transport layers on adjacent pixels to prevent charge leakage.

Vertically stacked atomically thin MoS2 and SWCNT layers form a gate-tunable p-n heterojunction diode.

Segmenting the charge-trapping layer prevents unwanted charge migration between adjacent memory cells, resolving data retention issues in vertical NAND arrays.

A semiconductor multilayer reflection mirror with a partially oxidized distributed Bragg reflector and conductive region enhances carrier injection efficiency.

A compact opto-electronic module uses a passive optical component with adjustable transmittivity to control light intensity distribution.

An aluminum nickel alloy forms data lines and electrodes in display panels to reduce chemical reactivity during dry etching.

A display module uses a translucent second light-emitting member to transmit light through the screen.

Non-conductive regions in sub-electrodes overlap touch leads to lower capacitance, resolving voltage drop and signal detection issues.

A compact EMI shield merges with the redistribution structure to block electromagnetic radiation from reaching the imaging die.

Alternately stacked charge trapping layers with distinct energy band gaps create internal barriers that confine electrical charges within the device structure.

Varying insulating film densities mitigate surface steps and defects, reducing moisture transmission to improve device reliability.

Gradually varied stripe electrode angles create multi-domain alignment to eliminate color shift at large viewing angles.

A 3D memory structure forms components within a substrate recess to isolate high-temperature fabrication steps from adjacent circuitry.

Conductive spacers protect phase change materials from degradation during read, set, and reset operations to maintain stable electrical properties.

Dual threshold GaN transistors merge diode functionality into the switching structure, eliminating complex separate over-voltage protection integration.

A Fin-FET passivation layer forms simultaneously across active and isolation regions using one chemical mechanical polish step.

Curved scintillator layer corners absorb impact forces, preventing defects and maintaining detection quality in thin X-ray devices.

A nitride semiconductor light-emitting element uses a graded n-type electron-injection layer to confine charge carriers within the active region.

An insulating tunneling layer mediates electron transport between perovskite and the collection electrode.

PECVD transparent semiconductor layers in OLED anodes optimize luminous efficiency while eliminating multiple fine metal masks to reduce manufacturing costs.

Merging a storage capacitor electrode with an auxiliary power line reduces structural complexity and enhances capacitance for high-resolution displays.

A light-emitting diode device uses a partition layer to separate phosphor layers and electrically insulate adjacent cells.

Nitrogen plasma treatment lowers annealing temperature requirements while maintaining amorphous-crystalline structure for high mobility.

Patterned shield layer with dielectric-filled apertures reduces electrical interference in capacitive sensors.

An LED unit uses an anodized aluminum base and transparent paste to mount chips, resolving heat release issues while maintaining assembly simplicity.

Metal pillars bridge carrier and transparent substrates to electrically connect LEDs, eliminating planar wire bonding risks and reducing package volume.

Polyacene compounds paired with low permittivity organic binders deliver high charge carrier mobility in printed electronics.

Replacing crystalline ITO with transparent amorphous oxide reduces internal stress damage to the light-receiving layer and eliminates complex buffer layers.

A p-electrode uses two ITO layers with distinct oxygen contents to lower contact resistance and boost light transmittance.

A boron nitride liner protects phase change material during low temperature deposition.

Convex structures on the first inorganic packaging film disconnect the organic layer, stopping water and oxygen diffusion through damaged areas.

Non-uniform bus lengths compensate for signal distortion, maintaining data reliability during high-frequency DDR4 operations.

An interposer element extends laterally between detectors and integrated circuits, enabling four-sided butting while maintaining signal integrity.

High etch selectivity protects tunnel layers from damage, preserving data retention.

A thin hard mask enables precise patterning of conformal layers on protruding strips, resolving pattern stability issues during 3D device fabrication.

A head-mounted display integrates a reflective layer and light-separating film to minimize device thickness.

A hierarchical sub-pixel design enables normal operation even when individual light-emitting elements fail.

Side electrode defines a void around the memory element to enhance interface strength and reduce reset current magnitude.

Recessing conductive lines enables self-aligned via formation, reducing misalignment resistance and shorting risks.

A parallel LED light source uses branches with identical high internal series resistance to distribute current evenly.

Extraction of alignment functions into nested spacers reduces manufacturing complexity while maintaining axial lens precision.

A stepped bottom spin-orbit-torque electrode structure forms a magnetic tunnel junction pillar with precise vertical alignment.

Segmented insulating layers resolve height differences between cell and peripheral regions, enabling uniform planarization for vertical memory devices.

A TFT-LCD array substrate employs a partition groove to generate a suspended undercut, resolving photoresist edge adhesion issues during the lift-off process.

A segmented epitaxial pedestal reduces contact via height and parasitic resistance, resolving reliability issues in high-stack-density memory devices.

Segmented silicon-germanium layers relax strain without dislocation defects, enhancing carrier mobility in released heterojunction structures.

A microLED display panel divides its substrate into sub-regions to integrate dedicated drive circuits directly on the surface.

A display device uses a third electrode positioned between first and second electrodes to improve light emission efficiency.

Varying microlens heights across concentric regions correct focal length deviations and improve edge light collection efficiency.

Constraining diffusion layer surface active areas based on localized thermal effects enhances dopant activation while reducing circuit leakage current.

Reconfigurable memory pins switch between transmitting and receiving modes to enable high-speed point-to-point links while reducing capacitive loading.

A semiconductor light emitting device integrates a second electrode within the sidewall of the second semiconductor pattern to enhance structural density.

An inductive coil embedded in an insulating adhesive layer activates a semiconductor stack to enhance light emission efficiency.

Transparent conductive patches repair electrode defects in display panels, resolving adhesion issues that cause production scraps.

An embedded heater in a chalcogenide pillar generates localized heat to reduce reset current and control concentrated thermal stress.

Staggered columnar portions with higher lowermost coverage distribute stress to prevent cracks in the stacked semiconductor memory device.

Segmented power traces with connecting sub-traces reduce bottom border length while preventing trace breakage during bending.

Staggered bitline contacts increase packing density in stacked memory arrays without violating minimum active area requirements.

A rotating blade removes metal burrs from diced workpieces using an organic acid and oxidizing agent liquid.

Inert plasma treatment and carbonization modify ULK dielectric trench surfaces to form protective SiCNH layers.

Magnetic attraction between sheets replaces mechanical adhesion to prevent cracks caused by support member misalignment.

A load circuit integrates a PNPN structure to conduct electrostatic discharge currents between I/O terminals.

A semiconductor memory device integrates global word lines and bit lines using projection contact parts to simplify manufacturing steps.

Support parts limit the gap between the package cover plate and substrate to ensure consistent seal height and width without spacers.

A display panel with divided anodes emits light sideways from a vacancy area, enabling normal imaging through the under-screen camera zone.

Curved and stepped cavity surfaces improve light incident efficiency onto guide plates while elevated leads position elements for higher luminosity.

A photodetector structure uses a barrier region to resist minority carrier flow between absorption and collection zones.

Prevents unintentional shorts between adjacent silicon layers by performing preliminary 3D-specific verification before physical stacking.

Replacing acidic PEDOT:PSS with low-temperature processed metal oxides prevents quantum dot degradation while maintaining high external quantum efficiency.

Independent wire clamping assembly movement prevents retraction and vibration-induced flying, securing stable connections.

Embedded quantum dots impart negative resistance to thermal image sensors, eliminating complex MEMS packaging.

Active magnetic shielding uses sensor feedback to generate opposing fields, mitigating external interference risks that passive packaging cannot fully block.

A white light-emitting diode manufacturing process uses an expansion sheet to stretch chip spacing and apply a uniform synthetic resin coating.

Removes native oxide from amorphous silicon surface to prevent silver agglomeration during resistive memory cell fabrication.

Aligned semiconducting carbon nanotubes detect 1.5 to 30 THz radiation with high sensitivity and spectral resolution at room temperature.

Photolithography patterns organic emissive layers directly on substrates to define pixels without physical masks.

Segmented resistive films in an RRAM cell expand the operation window for reliable multi-bit data storage.

Segmenting gate oxide formation into two stages prevents thermal damage to the ONO structure, maintaining its processing window and electric performance.

A silicon-germanium heterojunction bipolar transistor uses a buried oxide layer to isolate substrate noise.

A connection structure in the pad region electrically links touch screen wirings on a flexible OLED substrate.

A semiconductor die singulation method uses varied carrier substrate temperature to separate backside layers via localized pressure.

Selective insulating layer patterns on bridge electrodes increase contact area between first and second electrodes in touch displays.

Segmented image sensor collects visible and infrared light separately using dedicated optical filters, reducing light loss and improving infrared intensity.

A multiple p-ohmic contact layer combines transparent conducting and nitride layers to enhance light transmittance in top emission devices.

A light emitting module uses a mesh conductor layer to connect LEDs with varying electrode heights.

Light sensing units detect luminance degradation in organic light-emitting devices, adjusting driving current to maintain display performance.

Lateral selective etching creates self-aligned conductors to reduce lithographic steps while maintaining vertical alignment precision.

Placing the sensor atop finished metal lines reduces photon reflection and deflection at dielectric interfaces, improving signal strength.

Carbon bridges reinforce the porous silicon oxide matrix, reducing resistive-capacitive delay while maintaining structural integrity.

A gate polysilicon layer with varying surface area and thickness profiles stabilizes voltage distribution across semiconductor device regions.

Atomic layer deposition deposits conformal oxide passivation on superconducting Josephson junctions.

Introducing an auxiliary light emitting layer with specific peak wavelengths compensates for microcavity-induced color shifts across varying viewing angles.

Stacked oxide semiconductor and conductive layers form a robust common connection portion in display panels.