Semiconductor Memory Device with Projection Contact Parts
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Solution Overview
Problem
Conventional ReRAM semiconductor memory devices require separate steps for forming bit line select and word line select transistors, leading to increased device size due to the need for additional wiring and contact areas as the number of word line layers increases.
Innovation Solution
The semiconductor memory device integrates the formation of global word lines and bit lines in the same step, using projection contact parts to prevent short circuits and eliminate the need for additional lead-out wiring, allowing for a more compact and efficient structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If word line select transistor is provided upwardly of the memory cell array with separate formation steps, then the transistor can be formed, but the device size increases due to additional lead-out wiring and contact parts
Solution Approach 1:
The patent merges the formation of word line select transistors with the memory cell array structure by providing them in the same layer and using a common bit line. This integration eliminates the need for separate lead-out wiring and contact parts, reducing device size while maintaining manufacturability.
Solution Approach 2:
The patent repositions the word line select transistor from above the memory cell array to the same layer, utilizing the lateral dimension along the bit line. This dimensional reorganization eliminates vertical stacking requirements and reduces the need for additional contact areas.
2Quantity of substance
If the number of word line layers is increased, then memory capacity is improved, but the contact part area increases leading to larger device size
Solution Approach 1:
The patent transitions from vertical contact arrangements to lateral connections along the bit line. By extending the bit line to connect multiple word line select transistors in the same layer, the design accommodates increased memory capacity without proportionally increasing contact part area.
Solution Approach 2:
The bit line serves multiple functions: it acts as a common connection for multiple word line select transistors and as a signal transmission line. This multi-functionality reduces the need for separate contact parts for each word line layer.
3Reliability
If separate formation steps are used for bit line select and word line select transistors, then each transistor can be optimized, but manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of bit line select and word line select transistors into a single manufacturing step by providing them in the same layer with a common bit line connection. This reduces manufacturing complexity while maintaining the ability to optimize each transistor's performance through shared process parameters.
Data Source
AI summary
A semiconductor memory device of an embodiment includes a memory cell array. The memory cell array comprises: a semiconductor layer extending in a first direction; a plurality of conductive layers that face a side surface of the semiconductor layer and are stacked in the first direction; a variable resistance film provided at an intersection of the semiconductor layer and one of the conductive layers; a plurality of contact parts provided at ends of the plurality of conductive layers in a second direction intersecting the first direction, respectively; and a plurality of conductive parts that extend in the first direction and are connected to the plurality of contact parts, respectively. At least one of the plurality of contact parts includes a projection part projecting in the second direction.