Vertical Memory Mold Planarization via Segmented Insulating Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing of vertical memory devices with vertical channels faces challenges in planarization due to height differences between cell and peripheral regions, making it difficult to achieve effective insulating interlayer planarization.
Innovation Solution
A method involving the sequential formation of insulating interlayers and planarization stop layers, followed by the alternation of insulation and sacrificial layers to form mold structures with stepped shapes, ensuring uniform height and facilitating planarization without residue, allowing for the formation of gate structures and memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a planarization process is performed on an insulating interlayer in a vertical memory device manufacturing, then the surface flatness is improved, but the process becomes difficult to perform effectively due to height differences between cell and peripheral regions
Solution Approach 1:
The substrate is divided into two distinct regions: a first region (peripheral region) and a second region (cell region). The insulating interlayer is formed with different heights in these regions, allowing separate processing approaches for each region. This segmentation enables the planarization process to be applied effectively only where needed while accommodating the height difference between regions.
Solution Approach 2:
Different structural characteristics are applied to different regions of the substrate. The first region receives a gate structure and has a higher insulating interlayer, while the second region has a lower insulating interlayer without a gate structure. This local differentiation allows the planarization process to work effectively on the second region while preserving the necessary height in the first region for peripheral circuit functionality.
2Adaptability or versatility
If the insulating interlayer height is maintained higher in the peripheral region for gate structure formation, then the gate structure formation is enabled, but the height difference prevents effective planarization
Solution Approach 1:
The manufacturing process is segmented into region-specific operations. The peripheral region (first region) maintains the higher insulating interlayer height necessary for gate structure formation, while the cell region (second region) undergoes planarization to achieve the lower height. This segmentation allows both requirements to be satisfied simultaneously in their respective regions.
Solution Approach 2:
The insulating interlayer is designed with local quality variations: higher height and gate structure in the peripheral region for circuit functionality, and lower height in the cell region for planarization and memory cell formation. This local differentiation resolves the contradiction by allowing each region to have the properties it needs for its specific function.
Data Source
AI summary
A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.