RRAM Cell With Segmented Resistive Liners For Multi-Bit Storage
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Solution Overview
Problem
Current RRAM devices face challenges in achieving multiple resistance-determined states for multi-bit data storage due to limited operation windows, necessitating resistive films with high resistance values.
Innovation Solution
The implementation of a resistive memory cell structure featuring a resistive layer sandwiched between two L-shaped liners with resistive materials on both ends, which are connected in series and parallel configurations, enhancing the resistance and operation window for multi-bit memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single resistive film is used in the RRAM cell, then the device structure remains simple, but the operation window is limited and multi-bit memory operations cannot be efficiently performed
Solution Approach 1:
The single resistive film is segmented into multiple separate resistive films (first resistive film and second resistive film) connected in series between the bottom electrode and top electrode. This segmentation creates distinct resistance regions that can be independently controlled, enabling multi-bit memory operations by selectively programming each resistive film to different resistance states (high or low resistance), thereby expanding the operation window from binary to multi-state memory functionality.
2Reliability
If the resistive film resistance value is increased to enable multi-bit operations, then the operation window expands, but the device requires more complex structures to achieve and maintain high resistance values
Solution Approach 1:
Multiple resistive films are merged in a series configuration within a single memory cell structure, combining their resistance effects to achieve high overall resistance values. The bottom electrode, resistive films, and top electrode are integrated into a unified structure where the series connection of resistive films multiplicatively increases the total resistance, enabling multi-bit operations without requiring external circuitry or complex control mechanisms.
3Reliability
If multiple resistive films are connected in series to increase resistance, then the operation window expands for multi-bit operations, but the device complexity and fabrication process become more complex
Solution Approach 1:
The fabrication process transitions from planar deposition to three-dimensional structure formation by creating vertically stacked resistive films between bottom and top electrodes. This dimensional transition allows multiple resistive films to be deposited in sequence along the vertical axis, with each film separated by dielectric layers, enabling series connection without increasing lateral footprint or requiring complex interconnect routing, thus simplifying the manufacturing process while achieving high resistance values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased resistance values, expanding the operation window and enabling efficient multi-bit memory operations by utilizing chalcogenide, magneto-resistive, and polymer materials, effectively addressing the limitations of existing RRAM devices.
Implementation Method 1
RRAM is a memory device using materials with variable electrical resistance characteristics in accordance with external influences. Since the resistance will not change even after the power source has been disconnected, RRAM is a non-volatile memory device.
Implementation Method 2
enabling efficient multi-bit memory operations by utilizing chalcogenide, magneto-resistive, and polymer materials
Implementation Method 3
enabling efficient multi-bit memory operations by utilizing chalcogenide, magneto-resistive, and polymer materials
Data Source
AI summary
A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.