ROM Cell Pair With Shared Bitline and Staggered Contacts
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Solution Overview
Problem
Existing ROM devices face challenges in maintaining the minimum active region density and optimizing density due to the removal of active regions when programming memory cells to store '1' values, leading to inefficient packing and potential violations of design rules.
Innovation Solution
The proposed ROM design includes memory cell pairs with a shared bitline configuration that maintains active regions even when both cells store '1' values, and employs staggered bitline contacts to increase packing density, allowing for a more compact cell structure without violating minimum active area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If active regions are removed to program memory cells to store '1' values, then memory programming is achieved, but minimum active region density requirements are violated
Solution Approach 1:
The patent introduces a vertical stacking dimension by placing first and second memory cell pairs at different heights above the substrate. The first memory cell pair is positioned at a first height, while the second memory cell pair is positioned at a second height greater than the first height. This three-dimensional arrangement allows memory cells to be programmed to store '1' values (requiring active region removal) without violating minimum active region density requirements, as the active regions are distributed across multiple vertical layers rather than being removed from a single plane.
2Productivity
If memory cells are densely packed to increase storage capacity, then device density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory array into multiple stacked layers, with each layer containing memory cell pairs that share common bit line contacts and ground contacts. This segmentation allows each layer to be independently designed and manufactured while contributing to the overall high-density memory structure. The common sharing of contacts between cell pairs further reduces the number of required interconnects, managing manufacturing complexity.
Solution Approach 2:
The patent implements universal contact structures where bit line contacts and ground contacts are shared between multiple memory cell pairs across different vertical layers. The common bit line contacts serve multiple cells simultaneously, and the ground contacts provide common reference potential for multiple cell pairs. This multi-functionality reduces the total number of contacts required, simplifying the manufacturing process while achieving high memory density through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures that the ROM meets the minimum active area density requirements and achieves a more densely packed memory array, enhancing the overall efficiency and performance of the device.
Implementation Method 1
when the first word line (WL0) is asserted high, the active region becomes conductive and couples the common drain and bit line (BL0) to the first source and ground wire (VSS0), thereby causing the bit line (BL0) to be pulled low
Data Source
AI summary
One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memory cell also includes a bitline configured to provide data from the first and second memory cells, wherein the bitline is electrically isolated from the common drain. Other methods and systems are also disclosed.