Semiconductor Light Emitting Device Sidewall Electrode Integration
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Solution Overview
Problem
Existing semiconductor light emitting devices face challenges in integrating electrodes efficiently, leading to reduced light emission efficiency due to the need for dedicated spaces for electrode formation and limited scalability.
Innovation Solution
A semiconductor light emitting device design where the second electrode surrounds and contacts the sidewall of the second semiconductor pattern without a dedicated space, using a conductive division pattern to connect with the first electrode, enhancing integration and reducing light loss by ensuring light is emitted upwardly rather than downwardly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated space is allocated for electrode formation in existing semiconductor light emitting devices, then the electrodes can be properly formed and connected, but the light emission efficiency is reduced due to space occupation and light loss
Solution Approach 1:
The patent merges the electrode formation process with the semiconductor layer structure by forming the second electrode within the second semiconductor layer rather than in a dedicated space. The second electrode is integrated into the semiconductor layer through selective etching and filling, allowing electrode functionality to be combined with the light emitting structure, thereby eliminating dedicated electrode spaces that would block light emission.
Solution Approach 2:
The patent transitions from planar electrode formation to three-dimensional integration by forming the second electrode within the vertical structure of the second semiconductor layer. This dimensional integration allows the electrode to be embedded within the layer rather than occupying surface or lateral space, enabling light to pass through without obstruction while maintaining electrical connection.
2Ease of manufacture
If traditional electrode formation processes are used, then electrodes can be formed on flat surfaces, but the manufacturing complexity and costs increase due to additional process steps
Solution Approach 1:
The patent segments the second semiconductor layer to form a cavity for the second electrode, then selectively fills the cavity with conductive material. This segmentation approach allows the electrode to be formed in-place within the semiconductor layer structure, eliminating the need for separate electrode formation processes and reducing overall manufacturing complexity.
Solution Approach 2:
The second semiconductor layer serves dual purposes: it provides the light emitting function and simultaneously houses the second electrode. The layer's own structure is modified to create the electrode cavity, and the electrode material is deposited directly within this cavity, allowing the semiconductor layer to 'self-serve' as both functional element and electrode substrate.
3Reliability
If electrodes are formed in dedicated spaces, then proper electrical connection is achieved, but the device scalability is limited due to space constraints
Solution Approach 1:
The second semiconductor layer is designed to perform multiple functions: light emission, structural support, and electrode housing. By making the semiconductor layer universal in its functionality, the device can be scaled and adapted without requiring additional dedicated spaces for electrodes, as the same layer structure serves all purposes.
Solution Approach 2:
The second electrode is nested within the second semiconductor layer, creating a hierarchical structure where the electrode is contained within the layer's volume. This nesting arrangement allows the electrode to be integrated within the existing structure without requiring additional external space, enabling better device scalability and adaptability.
Data Source
AI summary
A semiconductor light emitting device including at least one light emitting structure on a substrate, the at least one light emitting structure including a first semiconductor pattern, an active pattern, and a second semiconductor pattern sequentially stacked in a vertical direction substantially perpendicular to an upper surface of the substrate; a first electrode contacting a substrate-facing surface of the first semiconductor pattern; and a second electrode at least partially surrounding and contacting a sidewall of the second semiconductor pattern.