Pitch Scalable 3D NAND Memory With Self-Aligned Etched Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D memory structures face challenges in scalability and density due to manufacturing limitations, particularly in vertical structures where charge trapping and memory cell alignment require complex lithographic processes, limiting the density and scalability of 3D memory technologies.
Innovation Solution
A scalable 3D memory structure is developed with self-aligned word lines and channel lines, achieved through lateral selective etching without additional lithographic alignment steps, allowing for the formation of memory cells with voids between them, enabling efficient data storage and manufacturing processes that reduce the number of required lithographic steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vertical 3D memory structures with charge trapping structures on sidewalls are used, then memory cell function is achieved, but x-y scaling is limited due to complex lithographic alignment requirements
Solution Approach 1:
The patent transitions from vertical 3D memory structures to horizontal 3D memory structures, changing the primary dimension of memory cell arrangement from vertical to horizontal. This dimensional change eliminates the need for complex sidewall charge trapping structures while maintaining memory functionality, thereby reducing manufacturing complexity and improving scalability.
Solution Approach 2:
The patent removes the charge trapping structures from the sidewalls of vertical channels, extracting the essential memory cell function to a simplified horizontal configuration. This extraction eliminates the manufacturing complexity associated with forming and aligning sidewall structures while preserving the core memory storage capability.
2Quantity of substance
If deep trenches and holes are formed to increase data storage capacity, then density is improved, but manufacturing complexity increases and limits scalability
Solution Approach 1:
The patent changes the architecture from vertical stacking requiring deep trenches to horizontal layering with shallower structures. This dimensional transformation maintains high data storage capacity by increasing the number of memory cell levels in the horizontal plane while reducing the depth of individual trench formations, thereby improving manufacturability.
Solution Approach 2:
The patent segments the memory structure into multiple horizontal levels or planes stacked vertically, where each plane contains arrays of memory cells formed by intersecting word lines and channel lines. This segmentation allows incremental fabrication of each plane using standard lithographic techniques, avoiding the need for single deep trench formations and improving overall manufacturing ease.
3Quantity of substance
If the number of memory planes is increased to提高 density, then data storage capacity is improved, but scalability is limited due to accumulated manufacturing complexity
Solution Approach 1:
The patent divides the high-density memory structure into multiple identical or similar horizontal planes, each with the same simplified memory cell architecture. This segmentation into repeatable units allows systematic scaling by adding more planes without compounding manufacturing complexity, as each plane can be fabricated using the same process steps.
Solution Approach 2:
The patent creates a universal memory cell design that functions identically across all horizontal planes, with standardized word lines, channel lines, and charge storage regions. This universality enables consistent fabrication processes to be applied across multiple planes, improving scalability by eliminating the need for plane-specific manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the scalability and density of 3D memory structures by simplifying the manufacturing process, allowing for smaller feature sizes and higher data storage capacity with fewer lithographic steps, while maintaining alignment without additional alignment processes.
Implementation Method 1
achieved through lateral selective etching without additional lithographic alignment steps
Data Source
AI summary
A memory includes a plurality of levels of word lines interleaved with a plurality of levels of channel lines. Horizontal data storage levels are disposed between the plurality of levels of word lines and the plurality of levels of channel lines, the data storage levels including respective arrays of data storage regions in cross points of word lines and channel lines in adjacent levels of the plurality of levels of word lines and the plurality of levels of channel lines. Respective arrays of holes outside of the cross points are disposed in the channel line and word line levels. The channel lines and word lines have sides defined by undercut etch perimeters, along with air gaps or voids between the channel lines and word lines in each level. The word lines, bit lines and data storage nodes in each layer are vertically self-aligned.