Self-Aligned Via Formation Using Recessed Conductive Lines
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Solution Overview
Problem
Conventional via manufacturing techniques in integrated circuit (IC) manufacturing often result in misalignment of vias, leading to increased via resistance, potential shorting, decreased yield, and higher manufacturing costs due to the inability to provide full via self-alignment.
Innovation Solution
A method involving recessing conductive lines on an insulating layer, depositing a conformal liner, and etching through a hardmask and photoresist to form self-aligned vias, ensuring precise alignment and reducing misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via manufacturing techniques are used, then the manufacturing process is simple, but via misalignment occurs leading to increased via resistance and potential shorting
Solution Approach 1:
The patent applies preliminary action by recessing the conductive lines before forming the vias. This pre-positioning of the conductive lines at a lower elevation allows the via formation process to naturally align with the recessed lines, ensuring precise alignment before the actual via etching occurs. The recessed conductive lines serve as a pre-established reference for subsequent via formation steps.
Solution Approach 2:
The patent segments the via formation process into distinct stages: first forming recessed conductive lines, then depositing insulating layers, and finally forming vias through controlled etching. This segmentation allows each step to be optimized independently, with the recessed conductive lines serving as a template that guides the subsequent via formation, thereby achieving precise alignment through process decomposition.
2Productivity
If via self-alignment is not achieved, then manufacturing cost increases due to rework and lower yield, but implementing self-alignment requires additional process steps
Solution Approach 1:
The patent implements self-service through self-aligned via formation where the via alignment is automatically determined by the recessed conductive lines themselves. The recessed lines act as self-generated alignment references that guide the via formation process without requiring external alignment tools or additional masking steps. This self-aligning mechanism improves yield by eliminating misalignment errors while avoiding the need for complex external alignment systems.
Solution Approach 2:
By performing the recessing of conductive lines as a preliminary action before via formation, the patent creates a self-aligning structure that naturally guides subsequent via etching. This preliminary positioning eliminates the need for complex real-time alignment procedures during via formation, thereby improving manufacturing yield through automatic alignment while managing process complexity through sequential step organization.
3Reliability
If misalignment is not corrected, then via resistance increases and device reliability decreases, but implementing correction requires additional manufacturing steps
Solution Approach 1:
The patent prevents reliability issues by performing preliminary recessing of conductive lines that establishes precise alignment references before via formation. This proactive alignment establishment ensures that vias will be correctly positioned, preventing misalignment-induced reliability problems such as increased via resistance and potential shorting, while avoiding the need for corrective steps after via formation.
Solution Approach 2:
The self-aligned via formation process uses the recessed conductive lines as self-generated alignment guides that automatically ensure proper via positioning. This self-correcting mechanism inherently prevents misalignment-related reliability issues without requiring external intervention or additional correction steps, thereby improving device reliability while managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves fully self-aligned vias with lower resistance and capacitance, increasing device yield and reducing manufacturing costs by eliminating misalignment and shorting issues.
Implementation Method 1
The photoresist is removed to leave the hardmask with the first opening
Implementation Method 2
The second insulating layer is etched through the first opening to expose the liner in the recessed first conductive line
Data Source
AI summary
Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.