Charge Trapping Layer Energy Barriers for Nonvolatile Memory Retention
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Solution Overview
Problem
Conventional nonvolatile memory devices face challenges in maintaining charge retention and reliability due to lateral and vertical diffusion of charges, leading to reduced storage capacity and efficiency.
Innovation Solution
The proposed nonvolatile memory devices incorporate a charge trapping layer with alternately stacked first and second trapping layers having different energy band gaps, a deep trapping layer, and a high density trapping layer, which form energy barriers to prevent charge diffusion, enhancing charge retention and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional charge trapping layer is used, then the device structure is simple, but charge diffusion occurs leading to poor charge retention and reduced reliability
Solution Approach 1:
The charge trapping layer is segmented into multiple distinct layers (first charge trapping layer, second charge trapping layer, third charge trapping layer) with different materials and energy band gaps. Each layer serves a specific function: the first layer (Si3N4) provides deep trap sites for strong charge retention, the second layer (SiO2) acts as a barrier to prevent charge diffusion, and the third layer (SiON) provides additional trap sites with intermediate energy levels. This segmentation resolves the contradiction by improving charge retention through functional specialization while managing the increased structural complexity through systematic design.
Solution Approach 2:
The invention employs composite materials by combining different dielectric materials (silicon nitride, silicon oxide, silicon oxynitride) with distinct energy band gaps and trap site characteristics within the charge trapping layer structure. Each material contributes unique properties: Si3N4 provides deep trap energy levels for strong charge confinement, SiO2 provides a wide band gap for charge isolation, and SiON provides intermediate properties. This composite approach improves charge retention by leveraging the complementary strengths of different materials while the systematic arrangement manages the complexity through material property optimization.
2Quantity of substance
If the trap site density is increased to improve storage capacity, then more charges can be stored, but charge diffusion and interference between adjacent charges increase
Solution Approach 1:
The invention applies local quality by creating regions with different trap site densities and energy levels within the charge trapping layer structure. The first charge trapping layer (Si3N4) has high trap site density for maximum charge storage capacity, while the second charge trapping layer (SiO2) has low trap site density but provides charge isolation through its wide band gap. The third layer (SiON) provides intermediate properties. This spatial variation in local quality allows high storage capacity in specific regions while maintaining charge stability through isolation in other regions, resolving the contradiction between quantity and reliability.
Solution Approach 2:
The second charge trapping layer (SiO2) acts as an intermediary between the first and third charge trapping layers. It provides charge isolation through its wide band gap, preventing charge diffusion and interference between adjacent charges stored in the high-density first layer and the third layer. This intermediary layer enables high storage capacity in the outer layers while maintaining charge stability through the isolating function of the middle layer, effectively resolving the contradiction between storage capacity and charge stability.
3Reliability
If energy barriers are added to prevent charge diffusion, then charge retention improves, but the device structure and fabrication process become more complex
Solution Approach 1:
The invention merges multiple functions into the charge trapping layer structure by combining charge storage, charge isolation, and charge confinement functions within a single integrated layer system. The first, second, and third charge trapping layers work together as a unified structure where each layer contributes to both storage and isolation functions. This merging approach improves charge retention through the combined effect of multiple layers providing energy barriers and trap sites, while simplifying the overall device architecture compared to adding separate isolated components, thus managing fabrication complexity.
Solution Approach 2:
Each charge trapping layer serves multiple functions simultaneously: the first layer (Si3N4) provides both deep trap sites for charge storage and an energy barrier for charge confinement; the second layer (SiO2) provides charge isolation through its wide band gap while also serving as a structural separator; the third layer (SiON) provides additional trap sites with intermediate energy levels and contributes to overall charge confinement. This multi-functionality improves charge retention through the combined effects of storage and isolation capabilities in each layer, while the systematic design of these universal layers manages fabrication complexity by reducing the need for additional specialized components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces charge loss and improves reliability by preventing horizontal and vertical movement of charges, thereby enhancing storage capacity and program efficiency.
Implementation Method 1
a charge trapping layer with alternately stacked first and second trapping layers having different energy band gaps, a deep trapping layer, and a high density trapping layer, which form energy barriers to prevent charge diffusion
Implementation Method 2
a charge tunneling layer between the charge trapping layer and the substrate
Data Source
AI summary
A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer.


