Gate Polysilicon Layer Voltage Distribution for ESD Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with built-in resistors face issues such as reduced ESD capability due to uneven voltage distribution and potential etching defects, and thick insulating films that decrease capacitance and increase the risk of dielectric breakdown.
Innovation Solution
The semiconductor device incorporates a gate polysilicon layer with varying surface areas to distribute voltage and reduce unevenness, while also increasing capacitance and ESD capability by optimizing the thickness and permittivity of insulating films, and integrating the gate resistance within the MOSFET structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If built-in resistors are disposed to oppose the gate pad, then gate resistance is achieved to stabilize switching operation, but ESD capability is reduced due to uneven voltage distribution
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate polysilicon layer thickness profile. The thickness varies from a first thickness at a first position to a second thickness at a second position, allowing different regions to have different electrical characteristics. This enables the gate resistance to provide switching stability while the varying thickness distribution helps equalize voltage distribution during ESD events, thereby maintaining ESD capability.
2Reliability
If thick insulating films are used, then dielectric breakdown risk is reduced, but capacitance decreases
Solution Approach 1:
The patent applies parameter changes by modifying the thickness parameter of the gate polysilicon layer. By varying the thickness from a first thickness to a second thickness at different positions, the patent achieves optimal electrical characteristics. This parameter variation allows the structure to maintain adequate capacitance while managing dielectric stress, effectively balancing the trade-off between capacitance and dielectric breakdown resistance.
3Object-affected harmful factors
If gate polysilicon layer thickness is varied, then voltage distribution is improved and ESD capability enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent implements parameter changes through a controlled thickness variation of the gate polysilicon layer. The thickness transitions from a first thickness at a first position to a second thickness at a second position, creating the desired voltage distribution and ESD capability enhancement. This parameter variation can be achieved through standard semiconductor manufacturing techniques such as selective epitaxial growth or chemical vapor deposition with spatially controlled conditions, thereby managing manufacturing complexity while achieving the performance benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances ESD tolerance, reduces defects from etching, and increases yield by distributing voltage and capacitance effectively, while maintaining the resistance value of the gate resistance.
Implementation Method 1
a gate polysilicon layer including a gate resistance, and having a second surface area in a plan view, the gate polysilicon pad facing the gate pad in a depth direction
Implementation Method 2
increasing capacitance and ESD capability by optimizing the thickness and permittivity of insulating films
Implementation Method 3
the oxide film being disposed between the semiconductor substrate and the gate polysilicon layer
Data Source
AI summary
A gate pad is includes a first portion disposed in a gate pad region and a second portion disposed in a gate resistance region and connected to the first portion, the gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer disposed on a front surface of a semiconductor substrate via a gate insulating film, between the semiconductor substrate and an interlayer insulating film, has a surface area at least equal to that of the gate pad and opposes an entire surface of the gate pad in a depth direction. ESD capability of a first region where the gate pad is provided is greater than ESD capability of a second region where a gate resistance is provided and is greater than ESD capability of a third region where a MOS structure of an active region is provided.