Stacked Semiconductor Memory Device Stress Distribution
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Solution Overview
Problem
In three-dimensional nonvolatile memory devices, maintaining the structural integrity of stacked wiring layers is challenging due to stress and bending risks, particularly in configurations with gaps between layers, which can lead to cracks and reduced durability.
Innovation Solution
The semiconductor memory device employs a stacked body with a stepped portion and columnar portions arranged in a staggered pattern, where the columnar portions in the lowermost step have a higher coverage than those in upper steps, effectively distributing stress and reducing the risk of cracks by relaxing external stress through their arrangement and material configuration similar to the pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If a stacked body with gaps between wiring layers is used to reduce stress, then the bending risk is reduced, but the structural strength and durability deteriorate due to crack propagation
Solution Approach 1:
The patent divides the stacked body into multiple segments by introducing gaps between wiring layers. These gaps segment the continuous structure into discrete layers, allowing stress to be distributed and released at each gap interface, preventing stress accumulation that would lead to cracking and maintaining structural integrity.
Solution Approach 2:
The patent incorporates gap structures in advance during the manufacturing process to serve as stress-cushioning elements. These pre-designed gaps act as cushioning zones that absorb and dissipate mechanical stress before it can propagate through the entire stacked body, preventing crack formation and maintaining durability.
2Strength
If columnar portions are added to support the stacked body, then structural strength is improved, but device complexity increases
Solution Approach 1:
The columnar portions serve multiple functions simultaneously: they provide mechanical support to maintain the stacked body structure, act as spacers to maintain consistent gap distances between wiring layers, and function as anchoring points for interlayer connections. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the support function with the spacing function by integrating the columnar portions into the existing layered structure. Rather than adding separate support elements and separate spacing elements, the columnar portions combine both functions into a single structural feature, simplifying the overall device architecture.
3Reliability
If coverage of columnar portions in lowermost step is increased to distribute stress, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different coverage requirements to different regions of the stacked body. The lowermost step, which bears the greatest mechanical load and experiences the highest stress concentration, is assigned a higher columnar portion coverage (70-90%). Upper steps have progressively lower coverage requirements. This localized quality approach optimizes reliability where needed while reducing manufacturing precision requirements in less critical areas.
Solution Approach 2:
The patent varies the coverage parameter of columnar portions across different steps of the stacked body. By changing the coverage parameter from high (70-90%) in the lowermost step to lower values in upper steps, the design achieves optimal stress distribution and reliability while accommodating manufacturing precision capabilities at each level.
Data Source
AI summary
A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.