Memory Module Bus Length Adjustment for Signal Integrity
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Solution Overview
Problem
High-speed operations in data processing systems face challenges in maintaining signal integrity due to signal distortion caused by higher operating frequencies, particularly in memory modules with synchronous dynamic random access memory (SDRAM) technologies like DDR2 and DDR3.
Innovation Solution
A memory module design featuring a specific bus structure where the bus length between certain nodes is longer than between adjacent nodes, incorporating a buffer chip to control operations, and using DDR4 type SDRAMs packaged in mono, dual, or stacked die structures with through silicon vias (TSVs), ensuring signal integrity by reducing signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating frequency of memory devices is increased to increase operating speeds, then productivity is improved, but signal integrity deteriorates due to signal reflection and interference
Solution Approach 1:
The patent applies local quality by making different portions of the bus have different lengths. Specifically, the bus includes a first portion with a first length and a second portion with a second length that is different from the first length. This non-uniform distribution of bus lengths compensates for signal distortion that occurs at high operating frequencies, thereby maintaining signal integrity while enabling high-speed operations.
2Reliability
If bus length is increased to compensate for signal distortion, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments the bus into multiple portions with different lengths to compensate for signal distortion. The bus is divided into a first portion and a second portion, where each portion has a specifically designed length to address signal integrity issues at different locations along the bus, thereby managing complexity through structured segmentation.
Solution Approach 2:
Different portions of the bus are given different lengths tailored to their specific signal transmission needs. The first portion has a first length and the second portion has a second length, creating local variations in bus characteristics that optimize signal integrity without requiring complete redesign of the entire bus structure.
Data Source
AI summary
A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.